A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor package may include: a substrate; a first sub-semiconductor package disposed over the substrate, the first sub-semiconductor package including a first buffer chip and a first memory chip; and a second memory chip disposed over the first sub-semiconductor package, wherein the first buffer chip and the first memory chip are connected to each other using a first redistribution line, and wherein the first buffer chip and the second memory chip are connected to each other using a second bonding wire.

A mass transfer method includes providing a transfer unit and a semiconductor carrying unit connected therewith, removing an element supporting structure of the semiconductor carrying unit from micro semiconductor elements of the semiconductor carrying unit, partially removing the photosensitive layer to form connecting structures, connecting a package substrate with electrodes of the micro semiconductor elements, breaking the connecting structures to separate the micro semiconductor elements from the transfer substrate. A mass transfer device is also disclosed.

Described herein is a die-to-wafer bonding process that utilizes micro-transfer printing to transfer die from a source wafer onto an intermediate handle wafer. The resulting intermediate handle wafer structure can then be bonded die-down onto the target wafer, followed by removal of only the intermediate handle wafer, leaving the die in place bonded to the target wafer.

A display device is provided in an embodiment in the disclosure, including a subpixel region, a spacer, a light-emitting element, and a driving circuit. The spacer separates the subpixel region into a first region and a second region. The light-emitting element is located in at least one of the first region or the second region. The driving circuit is electrically connected to the first region and the second region, so as to drive the light-emitting element. A manufacturing method of the display device is also disclosed.

A method of transferring a micro device and an array of micro devices are disclosed. A carrier substrate carrying a micro device connected to a bonding layer is heated to a temperature below a liquidus temperature of the bonding layer, and a transfer head is heated to a temperature above the liquidus temperature of the bonding layer. Upon contacting the micro device with the transfer head, the heat from the transfer head transfers into the bonding layer to at least partially melt the bonding layer. A voltage applied to the transfer head creates a grip force which picks up the micro device from the carrier substrate.

Provide are a transfer system and a transfer method. The transfer system is configured to transfer chips and includes a temporary substrate and a transfer device. The temporary substrate has a first surface and a second surface opposite to each other. There is a first angle between the second surface and the first surface. The transfer device has a transfer substrate and a plurality of transfer heads provided on the transfer substrate. The transfer substrate has a third surface and a fourth surface opposite to each other, and there is a second angle between the fourth surface and the third surface. The plurality of transfer heads are located at intervals on the fourth surface, and a side surface of the above-mentioned transfer head that faces away from the transfer substrate is parallel to the fourth surface.

A method for transferring at least one chip, from a first support to a second support, includes forming, while the chip is assembled to the first support, an interlayer in the liquid state between, and in contact with, a front face of the chip and an assembly surface of a face of the second support and a solidification of the interlayer. Then, the chip is detached from the first support while maintaining the interlayer in the solid state.

A transfer device, and a manufacturing method, a detection method and a detection device of the transfer device are provided. The transfer device includes a transfer head. A colloidal crystal layer is formed on at least one bulge of the transfer head. Based on the characteristics that a Bragg reflection effect of a colloidal crystal microsphere structure can present different light colors, whether the bulge is abnormal or not is determined according to light reflected by the colloidal crystal layer on each bulge.

Disclosed herein is a method for manufacturing a semiconductor comprising mechanically connecting one or more separate semiconductor components to a common intermediate carrier, arranging the intermediate carrier with respect to a substrate so that, at least for a majority of the semiconductor components, at least one solder pad of a particular semiconductor component lies opposite a solder pad of the substrate associated therewith forming a solder joint, and connecting mutually assiocaited solder pads of the one or more semiconductor components and the substrate by melting and solidifying a solder material arranged between the mutually associated solder pads. A surface tension of the solder material between the mutually associated solder pads of the substrate and the one or more semiconductor components sets a predetermined position of the intermediate carrier relative to the substrate, in which the one or more semiconductor components assume a target position relative to the substrate.