A high-frequency module includes a circuit board including wiring patterns, a resin on an active element mounted on the circuit board and a side of the circuit board and sealing the active element, and connection conductors penetrating the resin from a surface of the resin and provided on a top surface of the active element. The active element includes a first connection electrode on a surface facing the circuit board, and a second connection electrode on a top surface opposite to the surface facing the circuit board. The first connection electrode is connected to a wiring pattern on the circuit board, and the second connection electrode is connected to the connection conductor and an outer electrode and is not connected to the wiring pattern.

Integration of self-biased magnetic circulators with microwave devices is disclosed herein. In microwave and other high-frequency radio frequency (RF) applications, a magnetic circulator can be implemented with a smaller permanent magnet. Aspects disclosed herein include a process flow for producing a self-biased circulator in an integrated circuit chip. In this regard, a magnetic circulator junction can be fabricated on an active layer of a semiconductor wafer. A deep pocket or cavity is formed in an insulating substrate under the active layer. This cavity is then filled with a ferromagnetic material such that the circulator junction is self-biased within the integrated circuit chip, eliminating the need for an external magnet. The self-biased circulator provides high isolation between ports in a smaller integrated circuit.

In an example, a communication module such as an optoelectronic communication module may include an integrated circuit (IC), an electrical interconnect, and an interposer circuit. The electrical interconnect may include a radio frequency (RF) interconnect or a direct current (DC) interconnect. The interposer circuit may be electrically coupled between the IC and the electrical interconnect.

A high-frequency module (1) includes a component (3a) mounted on an upper surface (2a) of a substrate (2), a second sealing resin layer (4) stacked on the upper surface (2a) of the substrate (2), a component (3b) mounted on a lower surface (2b) of the substrate (2), a first sealing resin layer (5) stacked on the lower surface (2b) of the substrate (2), and a first terminal assembly (6) and a second terminal assembly (7) that are mounted on the lower surface (2b) of the substrate (2). The first terminal assembly (6) is mounted on a four-corner portion of the substrate (2) and includes a connection conductor (6a) thicker than a connection conductor (7a) of the second terminal assembly (7).

A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than −20 dB.

Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

According to one embodiment, a semiconductor device includes a wiring board, a spacer board that is mounted on the wiring board and in which a power supply conductor layer and a ground conductor layer are provided, at least one first semiconductor chip that is mounted on the spacer board including a power supply layer electrically connected to the power supply conductor layer and a ground layer electrically connected to the ground conductor layer, and a second semiconductor chip that is mounted on the wiring board.

A lead frame for a hermetic RF chip package includes: a first capacitor unit formed of a conductive material in a rectangular shape having a width smaller than a length to receive an input of an RF signal applied to the package circuit; a first inductor unit connected to the first capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length; a second capacitor unit connected to the first inductor unit and formed of a conductive material in a rectangular shape having a width smaller than a length; and a second inductor unit connected to the second capacitor unit and formed of a conductive material in a rectangular shape having a width greater than a length to transfer an RF signal input through the first capacitor unit to the RF chip.

A switching device includes first to third layers laminated in sequence above a principal surface of a substrate, a plurality of input terminals, a plurality of output terminals, a plurality of switching circuits, and a plurality of channels. Each of the channels electrically connecting one of the plurality of input terminals and one of the plurality of output terminals with one of the plurality of switching circuits interposed therebetween. The plurality of channels include a first channel and a second channel that intersect with each other when the principal surface of the substrate is seen in a plan view. In an intersection area where the first and second channels intersect with each other, the first channel is disposed on the first layer, the second channel is disposed on the third layer, and none of the plurality of channels is disposed on the second layer.

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.