A method for manufacturing a device includes: providing a semiconductor substrate having an RF-device; providing a BEOL-layer stack on the first main surface of the semiconductor substrate; attaching a carrier structure to a first main surface of the BEOL-layer stack; removing a lateral portion of the semiconductor substrate which laterally adjoins the device region to expose a lateral portion of the second main surface of the BEOL-layer stack; and opening a contacting region of the BEOL-layer stack at the lateral portion of second main surface of the BEOL-layer stack.

A semiconductor package, a semiconductor device and a method for packaging the semiconductor device are provided. A semiconductor package includes a first conductive wire layer with a first mounting area and a second mounting area, an integrated circuit (IC), a radiation fin structure and an antenna. The first mounting area and the second mounting area do not overlap. The IC is disposed on a first surface of the first mounting area. The radiation fin structure is disposed on a second surface of the first mounting area. The antenna is disposed on the second mounting area.

A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

A storage device includes a substrate of a memory package and a first memory die. The substrate includes a controller and a first pin pad, the first pin pad being electrically connected to the controller and defining a data channel for data communications. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a redistribution layer electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

Loss reduction methods are described. A first transmission loss associated with signal transmission through a trace in a first circuit board design is determined. The trace is routed from an integrated circuit disposed on a circuit board to a circuit element disposed on the circuit board. It is determined that the first transmission loss is greater than a threshold transmission loss. The first circuit board design is altered to obtain a second circuit board design. In the second circuit board design, the trace is routed from the integrated circuit to a connector disposed on the circuit board, and the connector is electrically coupled to the circuit element by a cable. A second transmission loss associated with signal transmission between the integrated circuit and the circuit element in the second circuit board design is less than the threshold transmission loss.

A circuit system includes a circuit board. An integrated circuit is mounted on the circuit board, the integrated circuit including a plurality of pins. A trace-to-cable connector is mounted on the circuit board, the trace-to-cable connector configured to couple to a first cable of a first cable-type. A cable-to-cable connector is mounted on the circuit board, the cable-to-cable connector configured to couple the first cable to a second cable of a second cable-type. A first plurality of metal traces couple a first subset of the plurality of pins to the trace-to-cable connector.

Conductive structures in a microelectronic package and having a surface roughness of 50 nm or less are described. This surface roughness is from 2 to 4 times less than can be found in packages with conductive structures (e.g., traces) formed using alternative techniques. This reduced surface roughness has a number of benefits, which in some cases includes a reduction of insertion loss and improves a signal to noise ratio for high frequency computing applications. The reduced surface roughness can be accomplished by protecting the conductive structure r during etch processes and applying an adhesion promoting layer to the conductive structure.

A switching device includes first to third layers laminated in sequence above a principal surface of a substrate, a plurality of input terminals, a plurality of output terminals, a plurality of switching circuits, and a plurality of channels. Each of the channels electrically connecting one of the plurality of input terminals and one of the plurality of output terminals with one of the plurality of switching circuits interposed therebetween. The plurality of channels include a first channel and a second channel that intersect with each other when the principal surface of the substrate is seen in a plan view. In an intersection area where the first and second channels intersect with each other, the first channel is disposed on the first layer, the second channel is disposed on the third layer, and none of the plurality of channels is disposed on the second layer.

A radio frequency switch circuit is described including a radio frequency switch and a coupler. The radio frequency switch includes a first band switch circuit connected between a first signal port and a common port, and configured to switch a first band signal. The coupler includes a first coupling wiring, disposed adjacent to a signal wiring formed between the common port of the radio frequency switch and an antenna port, and configured to form a first coupling signal with the signal wiring. A resonant frequency of the first coupling wiring is based on an inductance of the first coupling wiring and a capacitance of the radio frequency switch.

A semiconductor package includes an integrated circuit (IC), a heat dissipation structure, a molding layer and an antenna. The IC is mounted on a first surface of a first redistribution layer (RDL). The heat dissipation structure is mounted on a second surface of the first RDL. The molding compound is disposed over the first surface of the first RDL. The antenna is disposed on the second surface of the first RDL, wherein the antenna is disposed side-by-side to the heat dissipation structure.