In one embodiment, a semiconductor device includes a first substrate with a transistor formed in a first active are, a first bonding pad electrically connected to the transistor and a first metal pad surrounding the first active area. A second substrate of a type that is different from the first substrate includes a passive circuit element in a second active area on a front surface, a second bonding pad electrically connected to the passive circuit element, a second metal pad surrounding the second active area, and a mounting pad on a back surface of the second substrate with a through-via electrically connecting the second bonding pad to the mounting pad. A first interconnection extends from the first bonding pad to the second bonding pad, and a second interconnection extends from the first metal pad to the second metal pad and surrounds the region through which the first interconnection extends.

A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.

The present invention includes a method for creating a system in a package with integrated lumped element devices and active devices on a single chip/substrate for heterogeneous integration system-on-chip (HiSoC) in photo-definable glass, comprising: masking a design layout comprising one or more electrical passive and active components on or in a photosensitive glass substrate; activating the photosensitive glass substrate, heating and cooling to make the crystalline material to form a glass-crystalline substrate; etching the glass-crystalline substrate; and depositing, growing, or selectively etching a seed layer on a surface of the glass-crystalline substrate on the surface of the photodefinable glass.

An electronics package is disclosed. The electronics package includes a first radio frequency (RF) substrate layer, a second RF substrate layer, and a plurality of conductive layers disposed adjacent to at least one of the first RF substrate layer and the second RF substrate layer and including an inner conductive layer disposed between and adjacent to both the first RF substrate layer and the second RF substrate layer. The inner conductive layer bonds the first RF substrate layer to the second RF substrate layer. The electronics package also includes a plurality of conductive interconnects extending through the first RF substrate layer and the second RF substrate layer and electrically coupled between at least two of the plurality of conductive layers.

This application provides a chip apparatus, including a die, a first bond pad, a second bond pad, and a first solder pad. The first bond pad and the second bond pad are disposed on an upper surface of the die. A first power module and a second power module are disposed in the die. The first power module is coupled to the first bond pad. The second power module is coupled to the second bond pad. The first solder pad is separately coupled to an external power supply of the chip apparatus, the first bond pad, and the second bond pad. According to the foregoing technical solution, isolation between different power modules is improved, and noise transmitted on a power supply path can be better filtered out. This improves power supply noise performance of the chip apparatus.

A microelectronics package assembly and process of making same are disclosed. The flange has an upper surface and a first coating disposed on the upper surface of the flange. The insulator has a bottom surface for mounting onto the flange and an upper surface opposite the bottom surface. A second coating is disposed on the bottom surface of the insulator and a third coating disposed on the upper surface of the insulator. The first coating, the second coating, and the third coating each have a thickness of less than or equal to 1 micron. At least one of the first coating, the second coating, and the third coating is applied via at least one of physical vapor deposition, atomic deposition, or chemical deposition.

A radar system is described. In accordance with one example implementation, the radar system comprises a passive coupler arrangement and also a first radar chip, a second radar chip and a third radar chip. The radar chips each comprise at least one external RF contact and also a local oscillator designed to generate an RF oscillator signal at least in a switched-on state. The external RF contacts of the radar chips are coupled via the coupler arrangement in such a way that, in a first operating mode, the RF oscillator signal can be transferred from the first radar chip via the coupler arrangement to the second radar chip and the third radar chip, and that, in a second operating mode, the RF oscillator signal can be transferred from the second radar chip via the coupler arrangement to the third radar chip.

A coplanar waveguide structure includes a dielectric layer disposed over at least a portion of a substrate and a planar transmission line disposed within the dielectric layer. In some instances, the planar transmission line can include a conductive signal line and one or more ground lines. In other instances, the planar transmission line may include a conductive stacked signal line and one or more stacked ground lines.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.