The present invention provides a chip redistribution structure and a preparation method thereof. The chip redistribution structure includes a chip body, and a first distribution layer and a second distribution layer which are connected to the chip body. A first pin and a second pin are disposed on the surface of the chip body. The chip redistribution structure further includes a dielectric layer disposed on the surface of the chip body, wherein the dielectric layer is recessed downwards to form a first window, a second window, and a groove communicated with the first window. The first window and the second window respectively correspond to the first pin and the second pin. The first distribution layer extends along the groove and is communicated with the first pin, and the second distribution layer is disposed above the dielectric layer and is communicated with the second pin. In the present application, the first distribution layer and the second distribution layer are disposed in a staggered manner along the height direction through the dielectric layer provided with the groove, so that the size limitation problem of an existing redistribution process is overcome, the redistribution density can be improved, and the risk of short circuit is reduced.

The present invention provides a chip redistribution structure and a preparation method thereof. The chip redistribution structure includes a chip body, and a first distribution layer and a second distribution layer which are connected to the chip body. A first pin and a second pin are disposed on the surface of the chip body. The chip redistribution structure further includes a dielectric layer disposed on the surface of the chip body, wherein the dielectric layer is recessed downwards to form a first window, a second window, and a groove communicated with the first window. The first window and the second window respectively correspond to the first pin and the second pin. The first distribution layer extends along the groove and is communicated with the first pin, and the second distribution layer is disposed above the dielectric layer and is communicated with the second pin. In the present application, the first distribution layer and the second distribution layer are disposed in a staggered manner along the height direction through the dielectric layer provided with the groove, so that the size limitation problem of an existing redistribution process is overcome, the redistribution density can be improved, and the risk of short circuit is reduced.

A method for manufacturing electronic chips includes forming, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, trenches laterally separating the integrated circuits. At least one metal connection pillar per integrated circuit is deposited on the side of the upper face of the substrate, and a protective resin extends in the trenches and on an upper face of the integrated circuits. The method further includes forming, from an upper face of the protective resin, openings located across from the trenches and extending over a width greater than or equal to that of the trenches, so as to clear a flank of at least one metal pillar of each integrated circuit. The integrated circuits are separated into individual chips by cutting.

A method for manufacturing electronic chips includes depositing, on a side of an upper face of a semiconductor substrate, in and on which a plurality of integrated circuits has been formed, a protective resin. The method includes forming, in the protective resin, at least one cavity per integrated circuit, in contact with an upper face of the integrated circuit. Metal connection pillars are formed by filling the cavities with metal. The integrated circuits are separated into individual chips by cutting the protective resin along cut lines extending between the metal connection pillars.

A semiconductor device includes: a lower structure; a redistribution insulating layer disposed over the lower structure; a redistribution conductive layer disposed over the redistribution insulating layer and electrically connected to a part of the lower structure, the redistribution conductive layer including a redistribution pad; and a protective layer covering the redistribution insulating layer and the redistribution conductive layer while leaving the redistribution pad exposed. The redistribution conductive layer includes a trench disposed adjacent to the redistribution pad, and a part of the protective layer fills the trench.

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

An integrated circuit (IC) package is described. The IC package includes a die, having a pad layer structure on back-end-of-line layers on a substrate. The die also includes a metallization routing layer on the pad layer structure, and a first under bump metallization layer on the metallization routing layer. The IC package also includes a patterned seed layer on a surface of the die to contact the first under bump metallization layer. The IC package further includes a first package bump on the first under bump metallization layer.

An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a substrate, a conductive trace, a passivation layer and an upper wiring. The conductive trace is disposed over the substrate. The conductive trace includes a body portion disposed on the substrate, and a cap portion disposed on the body portion, and the cap portion is wider than the body portion. The passivation layer covers the conductive trace. The upper wiring is disposed on the passivation layer and electrically connected to the cap portion of the conductive trace through an opening of the passivation layer.

An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a substrate, a conductive trace, a passivation layer and an upper wiring. The conductive trace is disposed over the substrate. The conductive trace includes a body portion disposed on the substrate, and a cap portion disposed on the body portion, and the cap portion is wider than the body portion. The passivation layer covers the conductive trace. The upper wiring is disposed on the passivation layer and electrically connected to the cap portion of the conductive trace through an opening of the passivation layer.

An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.