The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

The semiconductor device includes a semiconductor element, a first lead, and a second lead. The semiconductor element has an element obverse surface and an element reverse surface spaced apart from each other in a thickness direction. The semiconductor element includes an electron transit layer disposed between the element obverse surface and the element reverse surface and formed of a nitride semiconductor, a first electrode disposed on the element obverse surface, and a second electrode disposed on the element reverse surface and electrically connected to the first electrode. The semiconductor element is mounted on the first lead, and the second electrode is joined to the first lead. The second lead is electrically connected to the first electrode. The semiconductor element is a transistor. The second lead is spaced apart from the first lead and is configured such that a main current to be subjected to switching flows therethrough.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.

A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.

A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposite the active surface; an encapsulant encapsulating at least some portions of the first interconnection member and the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the semiconductor chip. The first interconnection member and the second interconnection member respectively include a plurality of redistribution layers electrically connected to the connection pads of the semiconductor chip, and the semiconductor chip has a groove defined in the active surface and between a peripheral edge of the semiconductor chip and the connection pads of the semiconductor chip.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip; and connection terminals disposed on the second interconnection member. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip, and a connection pad and a connection terminal are electrically connected to each other by a pathway passing through the redistribution layer of the first interconnection member.

A semiconductor package comprising a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip, wherein the first semiconductor chip includes a first semiconductor body, an upper pad structure, and a first through-electrode penetrating the first semiconductor body and electrically connected to the upper pad structure, and the second semiconductor chip includes a second semiconductor body, a lower bonding pad, and an internal circuit structure including a circuit element, internal circuit wirings, and a connection pad pattern disposed on the same level as the lower bonding pad, the upper pad structure includes upper bonding pads and connection wirings, the upper bonding pads are disposed at positions corresponding to the lower bonding pad and the connection pad pattern, and the internal circuit structure is electrically connected to the first through-electrode through at least one of the upper bonding pads and the connection wirings.

Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.

A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.