Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

A semiconductor package includes a semiconductor chip having at least one chip pad disposed on one surface thereof; a wiring pattern disposed on top of the semiconductor chip and having at least a portion thereof in contact with the chip pad to be electrically connected to the chip pad; and a solder bump disposed on outer surface of the wiring pattern to be electrically connected to the chip pad through the wiring pattern.

The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP to reduce failures that may result from the WLCSP being exposed to thermal cycling or the WLCSP being dropped.

In one embodiment, a semiconductor device includes a first substrate including first and second regions on its surface, a first control circuit on the first substrate in the first region, a first memory cell array above the first control circuit in the first region and connected to the first control circuit, and a first pad above the first memory cell array in the first region and connected to the first control circuit. The device further includes a second control circuit on the first substrate in the second region, a second memory cell array above the second control circuit in the second region and connected to the second control circuit, a second pad above the second memory cell array in the second region and connected to the second control circuit, and a connection line above the first and second memory cell arrays and connecting the first and second pads.

In some examples, a package comprises a die and a redistribution layer coupled to the die. The redistribution layer comprises a metal layer, a brass layer abutting the metal layer, and a polymer layer abutting the brass layer.

A semiconductor package includes an electrode pad arranged in a first direction parallel to an upper surface of a semiconductor chip, a first protective layer at least partially surrounding an edge of the electrode pad and having a first opening that is above the electrode pad, a second protective layer at least partially surrounding the first protective layer and having a second opening that is above the electrode pad, and a redistribution structure electrically connected to the electrode pad and covering at least a part of an upper surface of the second protective layer. A first width of the first opening in the first direction is equal to or greater than a maximum width of the redistribution structure in the first direction, and a second width of the second opening in the first direction is less than the maximum width of the redistribution structure in the first direction.

A semiconductor package including a semiconductor chip having a chip pad thereon; a first insulating layer; a redistribution line pattern on the first insulating layer; a redistribution via pattern through the first insulating layer to connect the chip pad to the redistribution line pattern; a second insulating layer covering the redistribution line pattern and including a first part having a first thickness and a second part having a second thickness. the second part being inward relative to the first part; a first conductive pillar through the first part and connected to the redistribution line pattern; a second conductive pillar through the second part and connected to the redistribution line pattern; a first connection pad on the first conductive pillar; a second connection pad on the second conductive pillar; a first connection terminal contacting the first connection pad; and a second connection terminal contacting the second connection pad.

A semiconductor device includes a semiconductor chip body having a surface on which a chip pad is disposed, a passivation layer covering the surface of the semiconductor chip body and providing a tapered hole revealing the chip pad, and a redistributed layer (RDL) structure disposed on the passivation layer. The RDL structure includes a first RDL interconnection portion spaced apart from the tapered hole and passing by the tapered hole and a second RDL overlapping pad portion configured to have a bottom portion contacting the revealed chip pad and configured to have a first side surface facing a side surface of the first RDL interconnection portion. A central portion of the first side surface of the second RDL overlapping pad portion extends toward the side surface of the first RDL interconnection portion such that the first side surface is curved.

A semiconductor device is provided. The semiconductor device includes a substrate, an insulating film, and a photo sensitive film. The substrate includes a semiconductor chip region and a scribe line region disposed along an edge of the semiconductor chip region. The insulating film includes a first portion disposed on the semiconductor chip region, a second portion disposed on the scribe line region and connected with the first portion, and a third portion disposed on the scribe line region and protruded in a first direction from the second portion. The photo sensitive film is disposed on the insulating film and has a sidewall exposed on the second portion of the insulating film. A first width of the third portion in a second direction perpendicular to the first direction decreases as a distance from the semiconductor chip region increases.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first bump and a first dummy bump between the chip and the substrate. The first bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, the first dummy bump is between the first bump and a corner of the chip, and the first dummy bump is wider than the first bump.