Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.

A method for manufacturing an integrated circuit package includes depositing a first layer of metal at a location of a first metal post that is for connecting an IC die to an external circuit. The method also includes depositing a second layer of metal at the location of the first metal post, and a first layer of metal at a location of a second metal post that is for connecting the IC die to an external circuit.

The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.

The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.

A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of redistribution lines, and bonding a first device die to the first plurality of redistribution lines. The first metal post and the first device die are encapsulated in a first encapsulating material. The first encapsulating material is then planarized. The method further includes forming a second metal post over and electrically connected to the first metal post, attaching a second device die to the first encapsulating material through an adhesive film, encapsulating the second metal post and the second device die in a second encapsulating material, planarizing the second encapsulating material, and forming a second plurality of redistributions over and electrically coupling to the second metal post and the second device die.

The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.