A semiconductor device includes a semiconductor die having a main surface, a rear surface, outer edge sides extending between the main and rear surfaces, and a first conductive bond pad disposed on the main surface, an electrically insulating mold compound body formed around the outer edge sides of the semiconductor die with the main surface of the semiconductor die exposed from an upper surface of the mold compound body, a first metallization layer formed on the upper surface of the mold compound body and on the main surface of the semiconductor die, and a first bond pad extension formed in the first metallization layer. The first bond pad extension overlaps with the upper surface of the mold compound body. The first bond pad extension is conductively connected with the first conductive bond pad. The first bond pad extension is an externally accessible point of electrical contact of the device.

A semiconductor package includes a first integrated circuit structure, a first encapsulation material laterally encapsulating the first integrated circuit structure, a first redistribution structure, a solder layer, a second integrated circuit structure, a second encapsulation material second laterally encapsulating the second integrated circuit structure and a second redistribution structure. The first integrated circuit structure includes a first metallization layer. The first redistribution structure is disposed over the first integrated circuit structure and first encapsulation material. The first metallization layer faces away from the first redistribution structure and thermally coupled to the first redistribution structure. The solder layer is dispose over the first redistribution structure. The second integrated circuit structure is disposed on the first redistribution structure and includes a second metallization layer in contact with the solder layer. The second redistribution structure is disposed over the second integrated circuit structure and the second encapsulation material.

A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a protective layer having material properties on a die active surface of a die; attaching (such as adhering) the die in which the die active surface is formed with the protective layer onto a carrier, the die active surface facing the carrier, and a die back surface of the die facing away from the carrier; forming an encapsulation layer having material properties to encapsulate the die; removing (such as stripping off) the carrier to expose the protective layer; and forming a conductive layer and a dielectric layer. The chip packaging method reduces or eliminates warpage in the panel packaging process, lowers a requirement on an accuracy of aligning the die on the panel, reduces a difficulty in the panel packaging process, and makes the packaged chip structure more durable, and thus the present disclosure is especially suitable for large panel-level package and package of a thin chip with a large electric flux.

A semiconductor package includes a semiconductor device including a first UBM structure, wherein the first UBM structure includes multiple first conductive strips, the first conductive strips extending in a first direction, multiple second conductive strips separated from and interleaved with the multiple first conductive strips, the second conductive strips extending in the first direction, wherein the multiple first conductive strips are offset in the first direction from the multiple second conductive strips by a first offset distance, and a substrate including a second UBM structure, the second UBM structure including multiple third conductive strips, each one of the multiple third conductive strips bonded to one of the multiple first conductive strips or one of the multiple second conductive strips.

A semiconductor device includes: a first semiconductor chip having a first pad and a second pad, a depression being formed in the second pad; an organic insulating film provided on the first semiconductor chip, the organic insulating film covering the depression and not covering at least a portion of the first pad; and a redistribution layer having a lower portion connected to the first pad and an upper portion disposed on the organic insulating film.

A substrate structure includes a substrate, an encapsulating layer and a redistribution structure. The substrate has a first surface. The encapsulating layer surrounds the substrate and has a first surface. The redistribution structure is disposed on the first surface of the substrate and the first surface of the encapsulating layer. A gap exists in elevation between the first surface of the substrate and the first surface of the encapsulating layer.

Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.

A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.