H01L2224/03001

Integrated circuit features with obtuse angles and method forming same

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES INCLUDING CAVITIES FILLED WITH A SACRIFICIAL MATERIAL
20200331750 · 2020-10-22 ·

Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

Micro device metal joint process

Metal-to-metal adhesion joints are described as a manner to hold down micro devices to a carrier substrate within the context of a micro device transfer manufacturing process. In accordance with embodiments, the metal-to-metal adhesion joints must be broken in order to pick up the micro devices from a carrier substrate, resulting in micro devices with nubs protruding from bottom contacts of the micro devices. Once integrated, the micro devices are bonded to a receiving substrate, the nubs may be embedded in a metallic joint, or alternatively be diffused within the metallic joint as interstitial metallic material that is embedded within the metallic joint.

Micro device metal joint process

Metal-to-metal adhesion joints are described as a manner to hold down micro devices to a carrier substrate within the context of a micro device transfer manufacturing process. In accordance with embodiments, the metal-to-metal adhesion joints must be broken in order to pick up the micro devices from a carrier substrate, resulting in micro devices with nubs protruding from bottom contacts of the micro devices. Once integrated, the micro devices are bonded to a receiving substrate, the nubs may be embedded in a metallic joint, or alternatively be diffused within the metallic joint as interstitial metallic material that is embedded within the metallic joint.

Methods of fabricating semiconductor structures including cavities filled with a sacrificial material
10703627 · 2020-07-07 · ·

Methods of forming semiconductor structures comprising one or more cavities, which may be used in the formation of microelectromechanical system (MEMS) transducers, involve forming one or more cavities in a first substrate, providing a sacrificial material within the one or more cavities, bonding a second substrate over a surface of the first substrate, forming one or more apertures through a portion of the first substrate to the sacrificial material, and removing the sacrificial material from within the one or more cavities. Structures and devices are fabricated using such methods.

Integrated Circuit Features With Obtuse Angles and Method Forming Same
20200161260 · 2020-05-21 ·

A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.

Copper electroplating compositions and methods of electroplating copper on substrates

Copper electroplating compositions which include a diimidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features.

Semiconductor devices and semiconductor packages including the same, and methods of manufacturing the semiconductor devices

A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

Method for wafer level packaging
10573610 · 2020-02-25 · ·

Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu.sup.++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.

Method for wafer level packaging
10573610 · 2020-02-25 · ·

Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu.sup.++ to Cu. Metal traces are formed in trace channels within the first layer of catalytic adhesive. The trace channels extend below a surface of the first layer of the catalytic material. The trace metals traces are also in contact with integrated circuit pads on the surface of the wafer.