A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

An integrated circuit interconnects are described herein that are suitable for forming integrated circuit chip packages. In one example, an integrated circuit interconnect is provided that includes a first substrate containing first circuitry, a first contact pad, a first pillar, a first pillar protection layer, a second substrate containing second circuitry, and a solder ball disposed on the first pillar and electrically and mechanically coupling the first substrate to the second substrate. The first contact pad is disposed on the first substrate and coupled to the first circuitry. The first pillar electrically disposed over the first contact pad. The first pillar protection layer is hydrophobic to solder and is disposed on a side surface of the first pillar.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a metallization (13) of the TSV, an under-bump metallization (5) and a bump contact (6) at least partially covering the TSV at the further main surface. The TSV (3) comprises a cavity (15), which may be filled with a gas or liquid. An opening (15) of the cavity is provided to expose the cavity to the environment.

The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a metallization (13) of the TSV, an under-bump metallization (5) and a bump contact (6) at least partially covering the TSV at the further main surface. The TSV (3) comprises a cavity (15), which may be filled with a gas or liquid. An opening (15) of the cavity is provided to expose the cavity to the environment.

A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block.

An integrated device includes a semiconductor body and a dielectric layer bounded by a surface. A conductive region of a first metal material forms a via region extending into a hole passing through the dielectric layer, and an overlaid redistribution region which extends over the surface. At least one barrier region of a second metal material extends into the hole and surrounds the via region, and the barrier region furthermore extending over the surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the surface. A second coating layer of a fourth metal material extends at a distance from the surface and covers the first coating layer, and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier region extending over the surface.

An integrated device includes a semiconductor body and a dielectric layer bounded by a surface. A conductive region of a first metal material forms a via region extending into a hole passing through the dielectric layer, and an overlaid redistribution region which extends over the surface. At least one barrier region of a second metal material extends into the hole and surrounds the via region, and the barrier region furthermore extending over the surface. A first coating layer of a third metal material covers the top and the sides of an upper portion of the redistribution region at a distance from the surface. A second coating layer of a fourth metal material extends at a distance from the surface and covers the first coating layer, and covers laterally a lower portion of the redistribution region which is disposed on top of portions of the barrier region extending over the surface.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.