Bonded structures having conductive features and isolation features are disclosed. In one example, a bonded structure can include a first element including a first insulating layer and at least two first conductive features disposed in the first insulating layer. The bonded structure can also include a second element including a second insulating layer and at least two second conductive features disposed in the second insulating substrate. The first element can be directly bonded to the second element with the at least two first conductive features aligned with the at least two second conductive features. The bonded structure can also include an isolation feature in the second insulating layer and between the at least two second conductive features. The isolation feature can have a dielectric constant lower than a dielectric constant of the second insulating layer.

An integrated circuit has corner regions and non-corner regions between the corner regions and includes a semiconductor substrate, conductive pads, passivation layer, post-passivation layer, first conductive posts, and second conductive posts. The conductive pads are disposed over the semiconductor substrate. The passivation layer and the post-passivation layer are sequentially disposed over the conductive pads. The first conductive posts and the second conductive posts are disposed on the post-passivation layer and are electrically connected to the conductive pads. The first conductive posts are disposed in the corner regions and the second conductive posts are disposed in the non-corner regions. Each of the first conductive posts has a body portion and a protruding portion connected to the body portion. A central axis of the body portion of the first conductive post has an offset from a central axis of the protruding portion of the first conductive post.

A method of manufacturing a semiconductor package includes bonding first the and second structures, such that a first bonding structure is directly bonded to a second bonding structure. The forming of the first structure includes; forming a blocking layer on a metallic material layer including a first portion covering a concaved portion of the metallic material layer and a second portion covering a non-concaved portion of the metallic material layer, performing a first planarization process to remove the second portion of the blocking layer while the first portion of the blocking layer remains, performing a second planarization process to remove the non-concaved portion of the metallic material layer and expose the barrier layer on the insulating layer, performing a wet etching process to remove the barrier layer on the insulating layer and the blocking layer to form the first bonding pad including the barrier layer in the opening and the metallic material layer and forming a recessed portion below an upper surface of the metallic material layer on the barrier layer while removing the barrier layer on the insulating layer.

A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.

There are provided a stacked type semiconductor device and a manufacturing method of the stacked type semiconductor device. The stacked type semiconductor device includes: semiconductor chips stacked to overlap with each other; through electrodes respectively penetrating the semiconductor chips, the through electrodes being bonded to each other; and empty gaps respectively buried in the through electrodes.

A semiconductor die may be coupled to a printed circuit board using a solder ball. The semiconductor die comprises a redistribution layer formed above a semiconductor chip, a polymer layer formed on the redistribution layer, and an Under Bump Metallurgy (UBM) layer formed on the polymer layer. The polymer layer comprises a plurality of vias, which electrically couple the UBM layer to the redistribution layer. The entire UBM layer may be deposited with a continuously flat upper surface for coupling to the solder ball. The plurality of vias may be positioned such that they are centered on a point that is not central to the UBM layer.

Provided are a chip packaging method and a chip packaging structure. A passivation layer is provided on a pad of a wafer, a first metal bonding layer is then formed on the passivation layer, a second metal bonding layer is formed on a substrate, the substrate and the wafer are bonded and packaged together through bonding of the first metal bonding layer and the second metal bonding layer, a first shielding layer is provided on the substrate, and the first shielding layer is connected to the second metal bonding layer; and after the wafer and the substrate are bonded, semi-cutting is performed on the wafer until the first metal bonding layer is exposed, and a second shielding layer is then formed, and the second shielding layer is electrically connected to the first metal bonding layer, such that an electromagnetic shielding structure jointly composed of the first shielding layer, the second metal bonding layer, the second shielding layer and the first metal bonding layer is obtained. The shielding structure is thus approximately closed, thereby improving the electromagnetic shielding effect.

A semiconductor device includes: a semiconductor substrate having a first main surface; an aluminum electrode having a first surface facing the first main surface and a second surface opposite to the first surface, the aluminum electrode being disposed on the semiconductor substrate; a passivation film that covers a peripheral edge of the second surface and that is provided with an opening from which a portion of the second surface is exposed; a copper film disposed on the second surface exposed from the opening so as to be separated from the passivation film; and a metal film disposed on the second surface exposed from between the passivation film and the copper film. The metal film is constituted of at least one selected from a group consisting of a nickel film, a tantalum film, a tantalum nitride film, a tungsten film, a titanium film, and a titanium nitride film.

A curved light-emitting substrate and its formation method, and a display apparatus are provided in the present disclosure. The curved light-emitting substrate includes a substrate; an array layer, disposed on a side of the substrate; a plurality of light-emitting elements, electrically connected to the array layer, where a light-emitting element of the plurality of light-emitting elements includes a light-emitting main body and a first soldering pad on a side of the light-emitting main body facing the array layer; a second soldering pad which is on a side of the array layer facing the light-emitting element and electrically connected to the first soldering pad; and a flexible padding layer, between the light-emitting main body and the array layer along a first direction, where the first direction is perpendicular to a surface of the array layer.

A semiconductor device is obtained, in which the impact of bonding of the wiring member on an underneath structure including a semiconductor element is reduced and thus the reliability is improved. The semiconductor device includes: a semiconductor element with a first main surface; a first metal member formed on the first main surface; a second metal member formed on an upper surface of the first metal member; a third metal member formed on an upper surface of the second metal member; a fourth metal member with copper as a principal component, formed on an upper surface of the third metal member; and a wiring member with copper as a principal component, bonded to an upper surface of the fourth metal member corresponding to a formation position of the third metal member.