H01L2224/033

Textured bond pads

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

Stacked semiconductor structure and method

A device comprises a first chip comprising a first connection pad embedded in a first dielectric layer and a first bonding pad embedded in the first dielectric layer, wherein the first bonding pad comprises a first portion and a second portion, the second portion being in contact with the first connection pad and a second chip comprising a second bonding pad embedded in a second dielectric layer of the second chip, wherein the first chip and the second chip are face-to-face bonded together through the first bonding pad the second bonding pad.

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION
20210265206 · 2021-08-26 ·

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION
20210265206 · 2021-08-26 ·

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
20210125948 · 2021-04-29 ·

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, an intrinsically conductive pad positioned above the substrate, a stress relief structure positioned above the substrate and distant from the intrinsically conductive pad, and an external bonding structure positioned directly above the stress relief structure.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
20210125948 · 2021-04-29 ·

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, an intrinsically conductive pad positioned above the substrate, a stress relief structure positioned above the substrate and distant from the intrinsically conductive pad, and an external bonding structure positioned directly above the stress relief structure.

TEXTURED BOND PADS

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
20200395273 · 2020-12-17 ·

A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes an underlying semiconductor layer, an insulation layer, a first through semiconductor via, a second through semiconductor via, and an upper conductive connecting portion. The insulation layer is disposed over the underlying semiconductor layer. The first through semiconductor via extends continuously through the insulation layer. The first through semiconductor via has a first upper end above the insulation layer. The second through semiconductor via extends continuously through the insulation layer. The second through semiconductor via has a second upper end above the insulation layer. The upper conductive connecting portion is laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end.

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
20200395273 · 2020-12-17 ·

A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes an underlying semiconductor layer, an insulation layer, a first through semiconductor via, a second through semiconductor via, and an upper conductive connecting portion. The insulation layer is disposed over the underlying semiconductor layer. The first through semiconductor via extends continuously through the insulation layer. The first through semiconductor via has a first upper end above the insulation layer. The second through semiconductor via extends continuously through the insulation layer. The second through semiconductor via has a second upper end above the insulation layer. The upper conductive connecting portion is laterally connected to a first upper lateral surface of the first upper end and a second upper lateral surface of the second upper end.

Packaged Semiconductor Devices, Methods of Packaging Semiconductor Devices, and PoP Devices
20200312791 · 2020-10-01 ·

A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.