The present disclosure relates to a semiconductor chip, having an aluminium layer, wherein said aluminium layer has a structuration of at least a portion of a surface receiving an additional deposition of either copper or epoxy resin, and wherein said structuration forms peaks on said portion of surface occupying between 20 and 80% of said portion of surface.

In some embodiments, the present disclosure relates to a device that includes an interconnect structure arranged on a frontside of a substrate. The interconnect structure includes interconnect conductive structures embedded within interconnect dielectric layers. A trench extends completely through the substrate to expose multiples ones of the interconnect conductive structures. A bond pad structure is arranged on a backside of the substrate and extends through the trench of the substrate to contact the multiple ones of the interconnect conductive structures. A bonding structure is arranged on the backside of the substrate and electrically contacts the bond pad structure.

Electronic packages and package-on-package structures are described. In an embodiment, an electronic package include multiple staircased dies and multiple vertical wire bonds encapsulated by a molding layer, where the multiple vertical wire bonds protrude from a top surface of the molding layer so that the vertical wire bonds stand proud above a top surface of the molding layer.