Patent classifications
H01L2224/035
BONDED NANOFLUIDIC DEVICE CHIP STACKS
A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.
BONDED NANOFLUIDIC DEVICE CHIP STACKS
A method of producing a bonded chip stack is described. A first nanofluidic device chip having a first through-wafer via is formed. A second nanofluidic device chip having a second through-wafer via is formed. The first nanofluidic device chip and the second nanofluidic device chip are washed with a detergent solution. A first surface of the first nanofluidic device chip and a second surface of the second nanofluidic device chip are activated by treating the first surface and the second surface with an activation solution. The first nanofluidic device chip and the second nanofluidic device chip are arranged in a stack. The first through-wafer via is aligned with the second through-wafer via in a substantially straight line. The stack of first and second nanofluidic device chips is subjected to annealing conditions.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to an embodiment includes a substrate. An insulating film is provided above the substrate. Electrode pads are provided on the insulating film. Metallic bumps are respectively provided on surfaces of the electrode pads. A sidewall film comprises a metallic oxide or a metallic hydroxide provided on side surfaces of the metallic bumps. A barrier metal layer comprises first portions each provided between one of the metallic bumps and a corresponding one of the electrode pads and comprising a metal, and second portions provided at least on the electrode pads at a periphery of the metallic bumps and comprising a metallic oxide or a metallic hydroxide.
SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION
A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION
A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION
A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
SOLDERING A CONDUCTOR TO AN ALUMINUM METALLIZATION
A method of making a semiconductor including soldering a conductor to an aluminum metallization is disclosed. In one example, the method includes substituting an aluminum oxide layer on the aluminum metallization by a substitute metal oxide layer or a substitute metal alloy oxide layer. Then, substitute metal oxides in the substitute metal oxide layer or the substitute metal alloy oxide layer are at least partly reduced. The conductor is soldered to the aluminum metallization using a solder material.
Redistribution layer metallic structure and method
The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.
Redistribution Layer Metallic Structure and Method
The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.