A semiconductor device includes a surface metal formed on a substrate, a first protective film formed on the surface metal, a second protective film having a first portion provided on the first protective film and a second portion continuing to the first portion and provided on the surface metal and being transparent to light, and a metal film having a main body portion provided on the surface metal and a run-on portion continuing to the main body portion and running onto the first protective film, wherein the main body portion is thicker than the first protective film, the first portion is thicker than the run-on portion, and the second portion is thicker than the main body portion.

A method for bonding chips to a landing wafer is disclosed. In one aspect, a volume of alignment liquid is dispensed on a wettable surface of the chip so as to become attached to the surface, after which the chip is moved towards the bonding site on the wafer, the bonding site equally being provided with a wettable surface. A liquid bridge is formed between the chip and the bonding site on the substrate wafer, enabling self-alignment of the chip. Dispensing alignment liquid on the chip and not the wafer is advantageous in terms of mitigating unwanted evaporation of the liquid prior to bonding.

The method of manufacturing a connection structure of a semiconductor chip includes: preparing a semiconductor chip having a first surface having a connection pad disposed thereon and a second surface opposing the first surface and including a passivation layer disposed on the first surface and covering the connection pad; forming an insulating layer on the first surface of the semiconductor chip, the insulating layer covering at least a portion of the passivation layer; forming a via hole penetrating through the insulating layer to expose at least a portion of the passivation layer; exposing at least a portion of the connection pad by removing the passivation layer exposed by the via hole; forming a redistribution via by filling the via hole with a conductive material; and forming a redistribution layer on the redistribution via and the insulating layer.

According to one embodiment, a semiconductor device includes a semiconductor element having a substrate with at least two bending portions formed on a first side surface thereof. The two bending portions are displaced from each other in a first direction that is perpendicular to the first side surface of the substrate and parallel to a front surface of the substrate and in a second direction parallel to the front surface of the substrate and perpendicular to a top surface of the substrate. A rearmost portion of the first side surface is substantially perpendicular to the front surface.

A method for determining a bonding pad spacing on the surface of a bonding wire chip includes the steps of setting a loop height (K); selecting a capillary, measuring an expansion angle of a capillary sharp mouth (C); measuring the diameter of the capillary sharp mouth (T); measuring the hole diameter of the capillary (H); and determining a bonding pad spacing on the surface of a bonding wire chip (P). The formula is as follows: P=(T+H)/2+[tan(C/2)]*K. This method more accurately determines bonding pad spacing on the surface of a bonding wire chip, thereby providing a wider performance adjustment space. Additionally, problems, such as mutual inductance abnormalities caused by wire deformation or even by short circuits with other circuits due to the contact between a packaged capillary and a bonded wire can be lowered, thereby improving the working efficiency and reducing the number of times verification is performed.

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

Provided is a semiconductor device with higher reliability and longer life which can suppress an increase in production costs. A semiconductor device includes: a semiconductor element; a top electrode on an upper surface of the semiconductor element; and a conductive metal plate containing copper as a main component and solid-state diffusion bonded to the top electrode of the semiconductor element.

A semiconductor device includes a surface metal formed on a substrate, a first protective film formed on the surface metal, a second protective film having a first portion provided on the first protective film and a second portion continuing to the first portion and provided on the surface metal and being transparent to light, and a metal film having a main body portion provided on the surface metal and a run-on portion continuing to the main body portion and running onto the first protective film, wherein the main body portion is thicker than the first protective film, the first portion is thicker than the run-on portion, and the second portion is thicker than the main body portion.

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.