A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

Die-substrate assemblies having sinter-bonded backside via structures, and methods for fabricating such die-substrate assemblies, are disclosed. In embodiments, the method includes obtaining an integrated circuit (IC) die having a backside over which a backmetal layer is formed and into which a plated backside via extends. The IC die is attached to an electrically-conductive substrate by: (i) applying sinter precursor material over the backmetal layer and into the plated backside via; (ii) positioning a frontside of the electrically-conductive substrate adjacent the plated backmetal layer and in contact with the sinter precursor material; and (iii) sintering the sinter precursor material to yield a sintered bond layer attaching and electrically coupling the IC die to the frontside of the electrically-conductive substrate through the backmetal layer and through the plated backside via. The sintered bond layer contacts and is metallurgically bonded to the backside via lining.

A unit pixel including a first light emitting stack; a second light emitting stack disposed under the first light emitting stack, and having an area greater than that of the first light emitting stack; a third light emitting stack disposed under the second light emitting stack, and having an area greater than that of the second light emitting stack, in which at least one of the first through third light emitting stacks includes a side surface having an inclination angle within a range of about 30 degrees to about 70 degrees with respect to a first plane parallel to a top surface of the third light emitting stack.

A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.

A method includes forming a first dielectric layer on a first wafer, and forming a first bond pad penetrating through the first dielectric layer. The first wafer includes a first semiconductor substrate, and the first bond pad is in contact with a first surface of the first semiconductor substrate. The method further includes forming a second dielectric layer on a second wafer and forming a second bond pad extending into the second dielectric layer. The second wafer includes a second semiconductor substrate. The first wafer is sawed into a plurality of dies, with the first bond pad being in a first die in the plurality of dies. The first bond pad is bonded to the second bond pad.

An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.