Embodiments of three-dimensional (3D) memory devices with embedded dynamic random-access memory (DRAM) and methods for forming the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes an input/output circuit, an array of embedded DRAM cells, and an array of 3D NAND memory strings in a same chip. Data is transferred through the input/output circuit to the array of embedded DRAM cells. The data is buffered in the array of embedded DRAM cells. The data is stored in the array of 3D NAND memory strings from the array of embedded DRAM cells.

Three-dimensional (3D) memory devices with 3D phase-change memory (PCM) and methods for forming and operating the 3D memory devices are disclosed. In an example, a 3D memory device includes a first semiconductor structure including an array of NAND memory cells, and a first bonding layer including first bonding contacts. The 3D memory device also further includes a second semiconductor structure including a second bonding layer including second bonding contacts, a semiconductor layer and a peripheral circuit and an array of PCM cells between the second bonding layer and the semiconductor layer. The 3D memory device further includes a bonding interface between the first and second bonding layers. The first bonding contacts are in contact with the second bonding contacts at the bonding interface.

A package substrate includes: a core insulation layer having first and second package regions and a boundary region between the first and second package regions; a first upper conductive pattern in the first package region; a second upper conductive pattern in the second package region; a first insulation pattern on the core insulation layer to partially expose the first and second upper conductive patterns, wherein the first insulation pattern includes a first trench at the boundary region, and first reinforcing portions in the first trench; a first lower conductive pattern in the first package region; a second lower conductive pattern in the second package region; and a second insulation pattern on the core insulation layer to partially expose the first and second lower conductive patterns, wherein the second insulation pattern includes a second trench at the boundary region, and second reinforcing portions in the second trench.

A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1.sup.th verification operation is ended after a k.sup.th verification operation is ended in the n.sup.th write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the n.sup.th write loop is supplied to the word line before start of the k+1.sup.th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1.sup.th verification operation is shorter than a time from start of the first verification operation to end of the k.sup.th verification operation in the n.sup.th write loop.

A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.

Wafer processing techniques, or methods for forming semiconductor rides, are disclosed for fabricating plated pillar dies having die-level electromagnetic interference (EMI) shield layers. In embodiments, the method includes depositing a metallic seed layer over a semiconductor wafer and contacting die pads thereon. An electroplating process is then performed to compile plated pillars on the metallic seed layer and across the semiconductor wafer. Following electroplating, selected regions of the metallic seed layer are removed to produce electrical isolation gaps around a first pillar type, while leaving intact portions of the metallic seed layer to yield a wafer-level EMI shield layer. The semiconductor wafer is separated into singulated plated pillar dies, each including a die-level EMI shield layer and plated pillars of the first pillar type electrically isolated from the EMI shield layer.

There are provided a semiconductor module capable of preventing the peeling of a sealing resin on the side where a connection section used for the connection to a semiconductor element is arranged and a manufacturing method for a semiconductor module. A semiconductor module includes: an outer frame; sealing resins; gate signal output terminals, and partition sections laid across the outer flame to partition a space into a plurality of housing sections, in the partition sections which the gate signal output terminals with connection sections exposed are arranged. The partition sections have through holes where sealing resins are formed, the sealing resins connecting adjacent housing sections and the sealing resin formed in the through hole being continuous with the sealing resins formed in the housing sections.

A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

A semiconductor package includes a package substrate having a first side portion adjacent to a first edge, and a second side portion adjacent to a second edge opposite the first edge; a plurality of first substrate pads on the package substrate at the first side portion of the package substrate; a first chip on the package substrate; a second chip stacked on the first chip in a step-wise manner to result in a first exposure region exposing a portion of a surface of the first chip with respect to the second chip due to the step-wise stacking, the first exposure region being adjacent to a first edge of the first chip; a plurality of first bonding pads on a first portion of the first exposure region, the first portion of the first exposure region being adjacent to the first edge of the first chip; a plurality of second bonding pads on a second portion of the first exposure region, the second portion of the first exposure region further from the first edge of the first chip than the first portion of the first exposure region is to the first edge of the first chip, the plurality of second bonding pads being electrically insulated from any circuit components in the first chip; a plurality of third bonding pads on a surface of the second chip; and a plurality of bonding wires electrically connecting the third bonding pads to the first substrate pads via the second bonding pads.