A semiconductor package includes a semiconductor chip including a chip pad on a first surface thereof, an external pad electrically connected to the chip pad of the semiconductor chip, an external connection terminal covering the external pad, and an intermediate layer between the external pad and the external connection terminal, the intermediate layer including a third metal material that is different from a first metal material included in the external pad and a second metal material included in the external connection terminal.

A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip.

Cryogenic integrated circuits are provided. A cryogenic integrated circuit includes a thermally conductive base, a data processer, a storage device, a buffer device, a thermally conductive shield and a cooling pipe. The data processer is located on the thermally conductive base. The storage device is located on the thermally conductive base and disposed aside and electrically connected to the data processer. The buffer device is disposed on the data processer. The thermally conductive shield covers the data processer, the storage device and the buffer device. The cooling pipe is located in physical contact with the thermally conductive base and disposed at least corresponding to the data processer.

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

A structure and a formation method of a semiconductor device are provided. The method includes forming a passivation layer over a semiconductor substrate. The method also includes forming a magnetic element over the passivation layer. The method further includes forming an isolation layer over the magnetic element and the passivation layer. The isolation layer includes a polymer material. In addition, the method includes forming a conductive line over the isolation layer, and the conductive line extends across the magnetic element.

A semiconductor package includes a package substrate, a base module disposed on the package substrate and configured to include an intermediate chip, bonding wires connecting the intermediate chip to the package substrate, a lower-left chip disposed between the base module and the package substrate, and an upper-left chip disposed on the base module. The base module further includes an encapsulant encapsulating the intermediate chip, through vias electrically connected to the upper-left chip, and redistributed lines (RDLs) connecting the intermediate chip to the through vias and extending to provide connection parts which are spaced apart from the through vias and are connected to the lower-left chip.

A semiconductor package includes a package substrate, a lower chip, an interposer, and an upper chip which are stacked on the package substrate, and bonding wires electrically connecting the lower chip to the package substrate. The lower chip includes first and second lower chip pads spaced apart from each other on an upper surface of the lower chip, wire bonding pads bonded to the bonding wires on the upper surface of the lower chip, and lower chip redistribution lines electrically connecting the second lower chip pad to the wire bonding pad. The interposer includes an upper chip connection pad on an upper surface of the interposer, a lower chip connection pad on a lower surface of the interposer, and a through via electrode electrically connecting the upper chip connection pad to the lower chip connection pad.

A chip package module is provided. The chip package module includes a package substrate, a chip, and a conductive connector assembly. The chip having a first surface and a second surface opposite thereto is disposed on the package substrate. The first surface is divided into a first region, a second region, and a third region, and the second region is located between the first and third regions. The chip includes a flip-chip pad group disposed in the first region, a wire-bonding pad group disposed in the third region, and a signal pad group disposed in the second region. The conductive connector assembly is electrically connected between the chip and the package substrate. One of the flip-chip pad group and the wire-bonding pad group is electrically and physically connected to the conductive connector assembly, and the other one is not physically connected to the conductive connector assembly.

A physical quantity sensor includes a substrate, an acceleration sensor mounted on the substrate, an integrated circuit mounted on the substrate and stacked with the acceleration sensor, and serial communication wirings provided to the substrate. In a plan view of the acceleration sensor element, a bonding wire connecting the acceleration sensor element to the integrated circuit is disposed on an opposite side to the serial communication wirings with respect to a virtual central line of the acceleration sensor element.

An electronic component-incorporating substrate includes a lower substrate, an upper substrate, an electronic component located between the upper and lower substrates, a metal post connecting a first connection pad of the electronic component to a mounting pad of the lower substrate, a bonding wire connecting a second connection pad of the electronic component to a connection pad of the upper substrate, and an underfill resin filling the space between the electronic component and the lower substrate. The underfill resin covers the metal post and a first end of the bonding wire connected to the second connection pad of the electronic component. The bonding wire further includes a loop located at a lower position than a lower end of the metal post. The lower substrate further includes an accommodation portion that accommodates the loop.