A semiconductor device includes a substrate, input/output areas in a first direction and a second direction, parallel to an upper surface of the substrate and intersecting to each other, the input/output areas each including semiconductor elements providing an input/output circuit, lower wiring patterns connected to the semiconductor elements, and input/output pins connected to the lower wiring patterns, and bumps connected to the input/output pins by upper wiring patterns on the same layer as the input/output pins. The input/output areas include a first input/output area and a second input/output area, and each of the first input/output area and the second input/output area includes a first area and a second area sequentially in the first direction, and in the first input/output area, the input/output pin is in the first area, and in the second input/output area, the input/output pin is in the second area.

A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.

A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.

Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.

According to an aspect, a semiconductor device and an IO-cell include a plurality of first power supply lines and a plurality of second power supply lines alternately arranged in a first direction, the first and second power supply lines each being supplied with electric power in which the voltage of the electric power supplied to the first power supply is different from that supplied to the second power supply, and a third power supply line formed in a wiring layer different from a wiring layer in which the first and second power supply lines are arranged, the third power supply line being connected to adjacent first power supply lines among the plurality of first power supply lines through a via, in which all of the first, second and third power supply lines are formed so as to extend in a second direction perpendicular to the first direction.

A semiconductor device includes the following elements. A chip has a main surface substantially parallel with a plane defined by first and second directions intersecting with each other. A power amplifier amplifies an input signal and outputs an amplified signal from plural output terminals. First and second filter circuits attenuate harmonics of the amplified signal. The first filter circuit includes a first capacitor connected between the plural output terminals and a ground. The second filter circuit includes a second capacitor connected between the plural output terminals and a ground. On the main surface of the chip, the plural output terminals are disposed side by side in the first direction, and the first capacitor is disposed on a side in the first direction with respect to the plural output terminals, while the second capacitor is disposed on a side opposite the first direction with respect to the plural output terminals.

The present invention is directed to improving the bonding strength between a bonding wire and a lead frame bonded to a plurality of semiconductor devices electrically connected in parallel. One end and the other end of a first bonding wire are connected to a control electrode and a first lead frame portion or a bent portion of a first semiconductor device, and one end and the other end of a second bonding wire are connected to a control electrode and a second lead frame portion of a second semiconductor device. The first lead frame portion extends in a direction overlapping with the first semiconductor device from the bent portion toward the side opposite to the first semiconductor device side, and the second lead frame portion extends from the bent portion toward the second semiconductor device side in a direction overlapping with the second semiconductor device.

A semiconductor module comprises a first member including a semiconductor substrate made of a compound semiconductor and a first electronic circuit on the semiconductor substrate is mounted on a mounting surface of a module substrate, and a second member including a semiconductor layer formed of a single semiconductor thinner than the semiconductor substrate of the first member and a second electronic circuit on the semiconductor layer is bonded to an upper surface of the first member. First and second pads are respectively connected to the first electronic circuit on the first member and the second electronic circuit on the second member. A first wire connects the first pad and a substrate side pad. A second wire connects the second pad and a substrate side pad. An inter-member connection wire made of a conductor film on the first and second members connects the first and second electronic circuits.

A semiconductor device includes a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect.

Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.