A component mounting line includes a first and a second component mounting devices. The first component mounting device adheres anisotropic conductive members to a region of a part of one side and a region of the other side of the substrate, temporarily crimps electronic components onto the region of the part of the one side and the region of the other side to which the anisotropic conductive members are adhered, and mainly crimps the electronic components onto the region of the other side. The second component mounting device adheres the anisotropic conductive members to remaining regions of the one side of the substrate, temporarily crimps the electronic components onto the remaining regions of the one side to which the anisotropic conductive members are adhered, and mainly crimps the electronic components onto the region of the part of the one side and the remaining regions of the one side.

A semiconductor integrated circuit device with a PAD on I/O cell structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

A chip on film, including a base material provided with at least one row of output pads, wherein along an arranging direction of the output pads, an area where each row of output pads is located includes a first region, a second region and a third region, the second region is in the middle of the area where the row of output pads is located; the shape of each output pad located in the second region is different from the shape of each output pad located in the first region and the third region, and a maximum length spanned by each output pad located in the second region in the arranging direction is smaller than a minimum value among maximum lengths spanned by each output pad located in the first region and the third region in the arranging direction. A flexible display panel and a display device are further disclosed.

The present disclosure provides a semiconductor device including: a semiconductor chip including a circuit having a predetermined function, at least one first terminal connected to the circuit, and plural second terminals not connected to the circuit, the first and second terminals being formed along one edge of the semiconductor chip; plural third terminals provided at positions outside of the semiconductor chip and opposing the one edge, each of the plural third terminals being connected to one of the plural second terminals by a respective first wire; and an electronic component provided between the semiconductor chip and the third terminals, the electronic component including a fourth terminal that is connected to the first terminal by a second wire and is disposed below some of the first wires, wherein the first terminal is disposed at a position such that the first and second wires do not intersect.

A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

The disclosure generally relates to methods for manufacturing a filled gap region or cavity between two surfaces forming a device microchip. In one embodiment, the cavity results from two surfaces, for example, a PCB and a chip or two chips. More specifically, the disclosure relates to a method of manufacture and the resulting apparatus having porous underfill to enable rework of the electrical interconnects of a microchip on a multi-chip module. In one embodiment, the disclosure builds on the thermal underfill concept and achieves high thermal conductivity by the use of alumina fillers. Alternatively, other material such as silica filler particles may be selected to render the underfill a poor thermal conductive. In one embodiment, the disclose is concerned with reworkability of the material.

The disclosure generally relates to methods for manufacturing a filled gap region or cavity between two surfaces forming a device microchip. In one embodiment, the cavity results from two surfaces, for example, a PCB and a chip or two chips. More specifically, the disclosure relates to a method of manufacture and the resulting apparatus having porous underfill to enable rework of the electrical interconnects of a microchip on a multi-chip module. In one embodiment, the disclosure builds on the thermal underfill concept and achieves high thermal conductivity by the use of alumina fillers. Alternatively, other material such as silica filler particles may be selected to render the underfill a poor thermal conductive. In one embodiment, the disclose is concerned with reworkability of the material.

A semiconductor package that include first and second semiconductor chips bonded together, wherein the first semiconductor chip includes a first semiconductor substrate, a first semiconductor element layer and a first wiring structure sequentially stacked on a first surface of the first semiconductor substrate, first connecting pads and first test pads on the first wiring structure, and first front-side bonding pads, which are connected to the first connecting pads, wherein the second semiconductor chip includes a second semiconductor substrate, a second semiconductor element layer and a second wiring structure sequentially stacked on a third surface of the second semiconductor substrate, and first back-side bonding pads bonded to the first front-side bonding pads on the fourth surface of the second semiconductor substrate, and wherein the first test pads are not electrically connected to the second semiconductor chip.

An integrated circuit includes a transistor, and an impedance matching circuit coupled with the transistor. The impedance matching circuit includes a signal line to transmit a high-frequency signal and a power supply line that is a short stub branched from the signal line and supplies current to the transistor. The power supply line includes a bent line and a shortcut line to shortcut the bent line.

A semiconductor device includes a semiconductor layer that includes a semiconductor substrate having a first thickness and has a main surface, a main surface electrode that is arranged at the main surface and has a second thickness less than the first thickness, and a pad electrode that is arranged on the main surface electrode and has a third thickness exceeding the first thickness.