A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

A metallic etching process includes applying an anti-reflection coating over a metallic superstrate, applying a dry film photoresist over the anti-reflection coating, removing exposed portions of the dry film photoresist exposing a portion of the anti-reflection coating, etching the exposed portions of the anti-reflection coating exposing portions of the metal superstrate, etching portions of the metallic superstrate not covered by the dry film photoresist, and removing the dry film photoresist and the anti-reflection coating leaving portions of the metallic superstrate. An indium bump liftoff process includes applying a positive photoresist, forming a liftoff mask by applying a dry film photoresist over the positive photoresist, removing exposed portions of the liftoff mask to expose a portion of a substrate, depositing an indium film over the exposed portion of the substrate and remaining portions of the liftoff mask, and removing remaining portions of the liftoff mask.

A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

At least one circuit element may be formed on a front side of a ringed substrate, and the ringed substrate may be mounted on a mounting chuck. The mounting chuck may have an inner raised portion configured to receive the thinned portion of the substrate thereon, and a recessed ring around a perimeter of the mounting chuck configured to receive the outer ring of the ringed substrate therein. At least one solder bump may be formed that is electrically connected to the at least one circuit element, while the ringed wafer is disposed on the mounting chuck.

A method for forming a semiconductor structure includes following operations. A first substrate including a first side, a second side opposite to the first side, and a metallic pad disposed over the first side is received. A dielectric structure including a first trench directly above the metallic pad is formed. A second trench is formed in the dielectric structure and a portion of the first substrate. A sacrificial layer is formed to fill the first trench and the second trench. A third trench is formed directly above the metallic pad. A barrier ring and a bonding structure are formed in the third trench. A bonding layer is disposed to bond the first substrate to a second substrate. A portion of the second side of the first substrate is removed to expose the sacrificial layer. The sacrificial layer is removed by an etchant.

A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

A method for forming a semiconductor structure is provided. The method includes forming a seed layer over a substrate and forming a first mask layer over the seed layer. The method also includes forming a first trench and a second trench in the first mask layer and forming a first conductive material in the first trench and the second trench. The method further includes forming a second mask layer in the first trench and over the first conductive material, and forming a second conductive material in the second trench and on the first conductive material. A first conductive connector is formed in the first trench with a first height, a second conductive connector is formed in the second trench with a second height, and the second height is greater than the first height.

A light emitting device including at least one LED stack, electrode pads disposed on the LED stack, and cantilever electrodes disposed on the electrode pads, respectively, in which each of the cantilever electrodes has a fixed edge that is fixed to one of the electrode pads and a free standing edge that is spaced apart from the one of the electrode pads.

A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.