A method includes a first process in which a first wiring is provided on a surface of a semiconductor substrate; a second process in which a light transmitting substrate is attached to the surface; a third process in which the semiconductor substrate is thinned so that the thickness of the semiconductor substrate is smaller than the thickness of the light transmitting substrate; a fourth process in which a through hole is formed in the semiconductor substrate; a fifth process in which a dip coating method is performed using a resin material and thus a resin insulating layer is provided; a sixth process in which a contact hole is formed in the resin insulating layer; and a seventh process in which a second wiring is provided on a surface of the resin insulating layer, and the first wiring and the second wiring are electrically connected via a contact hole.

In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, ranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on the first electrode and a region other than the first electrode of the first surface, ranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.

An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

A test probe head for probe testing multiple chips on a wafer in a single probing. A probe head substrate includes an array of probe tip attach pads on one surface. The array includes a subarray for each probe head chip test site. Probe tips attached to each probe tip attach pad have an across the head tip height variation less than one micrometer (1 m). The subarray probe tips may be on a pitch at or less than fifty microns (50 m). The test probe head may be capable of test probing all chips in a quadrant and even up to all chips on a single wafer in a single probing.

An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.

A technique for fabricating bumps on a substrate is disclosed. A substrate that includes a set of pads formed on a surface thereof is prepared. A bump base is formed on each pad of the substrate. Each bump base has a tip extending outwardly from the corresponding pad. A resist layer is patterned on the substrate to have a set of holes through the resist layer. Each hole is aligned with the corresponding pad and having space configured to surround the tip of the bump base formed on the corresponding pad. The set of the holes in the resist layer is filled with conductive material to form a set of bumps on the substrate. The resist layer is stripped from the substrate with leaving the set of the bumps.