A system and method of using electrochemical additive manufacturing to add interconnection features, such as wafer bumps or pillars, or similar structures like heatsinks, to a plate such as a silicon wafer. The plate may be coupled to a cathode, and material for the features may be deposited onto the plate by transmitting current from an anode array through an electrolyte to the cathode. Position actuators and sensors may control the position and orientation of the plate and the anode array to place features in precise positions. Use of electrochemical additive manufacturing may enable construction of features that cannot be created using current photoresist-based methods. For example, pillars may be taller and more closely spaced, with heights of 200 ?m or more, diameters of 10 ?m or below, and inter-pillar spacing below 20 ?m. Features may also extend horizontally instead of only vertically, enabling routing of interconnections to desired locations.

An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3D joining of microelectronic components with a conductively self-adjusting anisotropic matrix. In an implementation, the adhesive matrix automatically makes electrical connections between two surfaces that have opposing electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

An adhesive with self-connecting interconnects is provided. The adhesive layer provides automatic 3D joining of microelectronic components with a conductively self-adjusting anisotropic matrix. In an implementation, the adhesive matrix automatically makes electrical connections between two surfaces that have opposing electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

A wafer level chip packaging method, comprising: 1) providing a carrier and forming a bonding layer on a surface of the carrier; 2) forming a dielectric layer on a surface of the bonding layer; 3) attaching each of semiconductor chips, with its front face facing down, to a surface of the dielectric layer; 4) packaging each of the semiconductor chips by using an injection molding process; 5) separating the bonding layer and the dielectric layer to remove the carrier and the bonding layer; 6) forming a redistribution layer for the semiconductor chips based on the dielectric layer; and 7) performing a reballing reflow process on the redistribution layer to form micro bumps. As a result, contamination in the semiconductor chips from the packaging process is greatly controlled, thereby improving the rate of finished products and the electrical property of the semiconductor chips.

A wafer level chip packaging method, comprising: 1) providing a carrier and forming a bonding layer on a surface of the carrier; 2) forming a dielectric layer on a surface of the bonding layer; 3) attaching each of semiconductor chips, with its front face facing down, to a surface of the dielectric layer; 4) packaging each of the semiconductor chips by using an injection molding process; 5) separating the bonding layer and the dielectric layer to remove the carrier and the bonding layer; 6) forming a redistribution layer for the semiconductor chips based on the dielectric layer; and 7) performing a reballing reflow process on the redistribution layer to form micro bumps. As a result, contamination in the semiconductor chips from the packaging process is greatly controlled, thereby improving the rate of finished products and the electrical property of the semiconductor chips.

A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

A pattern formed on a silicon wafer is fine so that solder bumps formed on the silicon wafer are also fine and hence, when a failure occurs, the failure cannot be corrected so that an entire silicon wafer as a workpiece is discarded. Provided is a correction method where, on solder bumps formed on the silicon wafer, a mask in which holes are formed with the same pattern as the solder bumps is placed so as to cover the solder bumps and, thereafter, molten solder is caused to come into contact with the solder bumps through the mask thus filling hole portions of the mask with the molten solder.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A microelectronic device has a bump bond structure including an electrically conductive pillar with an expanded head, and solder on the expanded head. The electrically conductive pillar includes a column extending from an I/O pad to the expanded head. The expanded head extends laterally past the column on at least one side of the electrically conductive pillar. In one aspect, the expanded head may have a rounded side profile with a radius approximately equal to a thickness of the expanded head, and a flat top surface. In another aspect, the expanded head may extend past the column by different lateral distances in different lateral directions. In a further aspect, the expanded head may have two connection areas for making electrical connections to two separate nodes. Methods for forming the microelectronic device are disclosed.