A method of fabrication of a semiconducting structure intended to be assembled to a second support by hybridisation. The semiconducting structure comprising an active layer comprising a nitrided semiconductor. The method comprises a step for the formation of at least one first and one second insert and during this step, a nickel layer is formed in contact with the support surface, and a localised physico-chemical etching step of the active layer, a part of the active layer comprising the active region being protected by the nickel layer.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond bump disposed on an upper surface of an upper conductive structure. The upper conductive structure overlies a substrate. A buffer layer is disposed along the upper surface of the upper conductive structure. The bond bump comprises a sidewall having a straight sidewall segment overlying a curved sidewall segment.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

A chip package may include a first polymer layer and a first semiconductor chip in the first polymer layer. The first semiconductor chip may include a first semiconductor device and a first semiconductor substrate supporting the first semiconductor device. The first semiconductor chip may also have a first contact pad coupled to the first semiconductor device. The first semiconductor chip may further include a first conductive interconnect on the first contact pad. The chip package may also include a second polymer layer on the first polymer layer and across an edge of the first semiconductor chip. The chip package may further include a first conductive layer in the second polymer layer and directly on a surface of the first conductive interconnect, and across the edge of the first semiconductor chip.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, and a bump disposed on the conductive pad, wherein the bump has a first top width and a bottom width, the first top width is greater than the bottom width, and a pair of spacers is disposed adjacent to the bump.