A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.

A bonding structure is provided, including a first substrate; a second substrate disposed opposite the first substrate; a first bonding layer disposed on the first substrate; a second bonding layer disposed on the second substrate and opposite the first bonding layer; and a silver feature disposed between the first bonding layer and the second bonding layer. The silver feature includes a silver nano-twinned structure including parallel twin boundaries. The silver nano-twinned structure includes 90% or more [111] crystal orientation. A method for forming a bonding structure is also provided. Each of steps of forming a first silver feature and second silver feature includes sputtering or evaporation coating. Negative bias ion bombardment is applied to the first silver feature and second silver feature during sputtering or evaporation.

An embodiment bonded integrated circuit (IC) structure includes a first IC structure and a second IC structure bonded to the first IC structure. The first IC structure includes a first bonding layer and a connector. The second IC structure includes a second bonding layer bonded to and contacting the first bonding layer and a contact pad in the second bonding layer. The connector extends past an interface between the first bonding layer and the second bonding layer, and the contact pad contacts a lateral surface and a sidewall of the connector.

A semiconductor package including a first substrate including a first bump pad and a filling compensation film (FCF) around the first bump pad; a second substrate facing the first substrate and including a second bump pad; a bump structure (BS) in contact with the first bump pad and the second bump pad; and a non-conductive film (NCF) surrounding the BS and between the first substrate and the second substrate, wherein the NCF covers an upper surface and an edge of the FCF.

A semiconductor package including a first substrate including a first bump pad and a filling compensation film (FCF) around the first bump pad; a second substrate facing the first substrate and including a second bump pad; a bump structure (BS) in contact with the first bump pad and the second bump pad; and a non-conductive film (NCF) surrounding the BS and between the first substrate and the second substrate, wherein the NCF covers an upper surface and an edge of the FCF.

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

During electro-oxidative metal removal on a semiconductor substrate, the substrate having a metal layer is anodically biased and the metal is electrochemically dissolved into an electrolyte. Metal particles (e.g., copper particles when the dissolved metal is copper) can inadvertently form on the surface of the substrate during electrochemical metal removal and cause defects during subsequent semiconductor processing. Contamination with such particles can be mitigated by preventing particle formation and/or by dissolution of particles. In one implementation, mitigation involves using an electrolyte that includes an oxidizer, such as hydrogen peroxide, during the electrochemical metal removal. An electrochemical metal removal apparatus in one embodiment has a conduit for introducing an oxidizer to the electrolyte and a sensor for monitoring the concentration of the oxidizer in the electrolyte.

A method includes forming a package component comprising forming a dielectric layer, patterning the dielectric layer to form an opening, and forming a redistribution line including a via in the opening, a conductive pad, and a bent trace. The via is vertically offset from the conductive pad. The conductive pad and the bent trace are over the dielectric layer. The bent trace connects the conductive pad to the via, and the bent trace includes a plurality of sections with lengthwise directions un-parallel to each other. A conductive bump is formed on the conductive pad.