An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filing at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

This document describes systems and techniques of a depth-adaptive mechanism for ball grid array dipping. In an aspect, a depth-adaptive mechanism having a tensioned mesh is positioned in a reservoir filled with flux. When solder balls of an integrated circuit component are dipped into the reservoir of flux, the solder balls are pressed up against the tensioned mesh. The tensioned mesh is configured to, first, elastically deform under the downward force applied by the solder balls and, second, provide an equal and opposite pushing force in order to facilitate solder ball extraction. In so doing, the solder balls of an integrated circuit component can be more easily extracted from flux when deep ball grid array dipping is performed.

Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector and the semiconductor substrate and covering the adhesive layer. An interface between the adhesive layer and the first buffer layer is substantially level with a bottom surface of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

A fan-out semiconductor package includes a core member having a through hole, at least one dummy structure disposed in the core member, a semiconductor chip disposed in the through hole and including an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of each of the core member and the semiconductor chip, and filling at least a portion of the through hole, and a connection member disposed on the core member and the active surface of the semiconductor chip, and including a redistribution layer electrically connected to the connection pad.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.

An integrated circuit structure includes a substrate, a metal pad over the substrate, a passivation layer having a portion over the metal pad, and a polymer layer over the passivation layer. A Post-Passivation Interconnect (PPI) has a portion over the polymer layer, wherein the PPI is electrically coupled to the metal pad. The integrated circuit structure further includes a first solder region over and electrically coupled to a portion of the PPI, a second solder region neighboring the first solder region, a first coating material on a surface of the first solder region, and a second coating material on a surface of the second solder region. The first coating material and the second coating material encircle the first solder region and the second solder region, respectively. The first coating material is spaced apart from the second coating material.