A semiconductor device includes: a first electrode provided on a semiconductor multilayer structure; a second electrode provided on a substrate; and a bonding metal layer which bonds the first electrode and the second electrode together. The bonding metal layer includes a gap inside.

An electronic component includes an electronic component main body including a first surface, a signal bump electrode arranged on the first surface to protrude from the first surface of the electronic component main body, and a protective film provided with an opening through which a part of the signal bump electrode is exposed, the protective film being arranged to cover a portion of the signal bump electrode other than a portion exposed through the opening. The protective film includes a first insulating film, a second insulating film that covers the first insulating film, and a first shield film arranged as lying between the first insulating film and the second insulating film. The first shield film is covered with at least one of the first insulating film and the second insulating film so as not to be exposed at an inner surface of the opening.

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the substrate. The chip package structure includes first conductive bumps arranged between and in direct contact with the chip package and the substrate providing a clearance. The chip package structure includes a chip structure having a first face and an opposing second face arranged in the clearance between the chip package and the substrate and adjacent to the first conductive bumps. The chip structure contains at least one chip. The chip package structure includes a solder cap connecting the first face of the chip structure and the chip package. The chip package structure includes a second conductive bump connecting the second face of the chip structure and the substrate.

An integrated circuit (IC) chip package includes a substrate and a wafer comprising an IC chip arranged on the substrate. The substrate includes first mounting pads unconnected to electrical connections in the substrate. The wafer includes second mounting pads that are disposed around corners of the IC chip, that extend radially outward relative to circuitry in the IC chip, that are unconnected to circuitry in the IC chip, and that mate with the first mounting pads on the substrate, respectively.

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

The invention provides a circuit substrate and a package structure. The circuit substrate includes a molding compound having a chip-side surface and a solder ball-side surface opposite from the chip side surface. A first conductive bulk is formed embedded in the molding compound. The first conductive bulk has a first number of first chip-side bond pad surfaces and a second number of first solder ball-side surfaces exposed from the chip side surface and the ball-side surface, respectively. The width of the first conductive bulk is greater than the first width of the first chip-side bond pad surfaces and the second width of the first solder ball-side surfaces.

A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

A multi-die package structure with an embedded die embedded in a substrate, and a flip chip die mounted above the substrate is discussed. The package is compact and low cost.

An embedded component substrate structure and a method for manufacturing the same, with a carrier structure being formed with a groove on a top, and a chip structure with a plurality of conductors disposed in the groove. Dielectric layers are disposed on a top and a bottom of the carrier structure, and two opposite ends of multiple circuits in the carrier structure are exposed to the dielectric layers. Circuit build-up structures are disposed on the dielectric layers, and electrically connect to the circuits of the carrier structure.