A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

A method of forming an integrated circuit (IC) package includes constructing a first power distribution structure on a first die included in the IC package, thereby electrically connecting the first power distribution structure to a second power distribution structure positioned on a back side of the first die, and bonding a third power distribution structure to the first power distribution structure, the third power distribution structure being positioned on a back side of a second die.

There are provided semiconductor packages including a redistribution substrate and a semiconductor chip mounted on the redistribution substrate. The redistribution substrate may include a lower protective layer, a first conductive pattern disposed on the lower protective layer, a first insulating layer surrounding the first conductive pattern and disposed on the lower protective layer, and a second insulating layer disposed on the first insulating layer. The first insulating layer may include a first upper surface that includes a first flat portion extending parallel to an upper surface of the lower protective layer, and a first recess facing the lower protective layer and in contact with the first conductive pattern. The first recess may be directly connected to the first conductive pattern.

A method for forming a chip package structure is provided. The method includes disposing a first chip structure and a second chip structure over a wiring substrate. The first chip structure is spaced apart from the second chip structure by a gap. The method includes disposing a ring structure over the wiring substrate. The ring structure has a first opening, the first chip structure and the second chip structure are in the first opening, the first opening has a first inner wall, the first inner wall has a first recess, and the gap extends toward the first recess.

A lead frame includes a lead frame substrate made of a copper-based material, plating layers composed of nickel, palladium and gold layers laminated in this order on top faces and bottom faces of the lead frame substrate, and a roughened silver plating layer having acicular projections, provided as an outermost plating layer and covering faces of the lead frame substrate that form concavities or a through hole between the top faces and the bottom faces of the lead frame substrate. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A lead frame includes a lead frame substrate made of a copper-based material, plating layers composed of nickel, palladium and gold layers laminated in this order on top faces and bottom faces of the lead frame substrate, and a roughened silver plating layer having acicular projections, provided as an outermost plating layer and covering faces of the lead frame substrate that form concavities or a through hole between the top faces and the bottom faces of the lead frame substrate. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111> and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering only top faces on the upper surface side of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction <101> occupies a largest proportion among the crystal directions <001>, <111>, and <101>. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a plurality of hollow vias extending through the package substrate. The semiconductor die is electrically connected to the package substrate. The hollow vias are disposed under the semiconductor die.

An electronic assembly is provided for communication between electronic chips. The electronic assembly include a mechanical support carrying at least one basic block, which includes at least two electronic chips. At least one of the electronic chips is configured as a data signaling chip with respect to at least one other electronic chips for data communication to said at least one other electronic chip, and said at least one other electronic chip is configured as a data receiving chip with respect to said data signaling chip. The data signaling and data receiving chips face one another by their surfaces, respectively, being arranged in a spaced-apart relationship and defining together at least one interface region. The data communication from the data signaling chip to the at least one data receiving chip is in the form of at least one flux of charge carriers in free space propagation via a gap between said spaced-apart surfaces of the chips in said interface region, to selectively operate the at least one data receiving chip dependent on an operative state of at least one of the electronic chips of the basic block.

An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.