Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/18
High density interconnect [HDI] connectors; Manufacturing methods related thereto
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H01L2224/20
Structure, shape, material or disposition of high density interconnect preforms
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H01L2224/22
of a plurality of HDI interconnects
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H01L2224/22

STACKED IMAGE SENSOR DEVICE AND METHOD OF FORMING SAME
20250366226 · 2025-11-27 ·

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first logic die including a first through via, an image sensor die hybrid bonded to the first logic die, and a second logic die bonded to the first logic die. A front side of the first logic die facing a front side of the image sensor die. A front side of the second logic die facing a backside of the first logic die. The second logic die comprising a first conductive pad electrically coupled to the first through via.

Stacked image sensor device and method of forming same
12484323 · 2025-11-25 · ·

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a first logic die including a first through via, an image sensor die hybrid bonded to the first logic die, and a second logic die bonded to the first logic die. A front side of the first logic die facing a front side of the image sensor die. A front side of the second logic die facing a backside of the first logic die. The second logic die comprising a first conductive pad electrically coupled to the first through via.