A semiconductor package includes a die pad having a die attach surface, a semiconductor die mounted on the die attach surface and having a first bond pad at an upper surface facing away from the die attach surface, an interconnect clip including a first segment which at least partially encloses a central opening, a second segment vertically offset and spaced apart from the first segment, and a support extending between the first segment and the second segment. The package further includes an electrically insulating encapsulant covering the semiconductor die. An upper surface of the first segment of the interconnect clip is exposed from a planar surface of the encapsulant. A lower surface of the second segment is flush against the upper surface of the semiconductor die and conductively connected to the first bond pad.

A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.

A clip for a semiconductor package includes a first portion and a second portion. The first portion includes a first surface, a second surface opposite to the first surface and configured to contact a first electrically conductive component, and a stepped region between the first surface and the second surface such that the second surface has a smaller area than the first surface. The second portion is coupled to the first portion and configured to contact a second electrically conductive component. The second portion includes a third surface aligned with the first surface.

A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.

An interconnect clip includes a die contact portion having planar upper and lower surfaces, a bridge portion adjoining the die contact portion and having planar upper and lower surfaces, a lead contact portion adjoining the bridge portion and having first and second planar lower surfaces that form an angled intersection with one another at a contact point, a first transition surface extending transversely from the lower surface of the bridge portion, and a second transition surface extending transversely from the lower surface of the bridge portion. The lower surface of the die contact portion extends along a first plane. The lower surface of the bridge portion extends from the first transition surface to the second transition surface along a second plane that is completely above the first plane. The first lower surface of the lead contact portion is tilted relative to the first plane.

An embodiment related to a stacked package is disclosed. The stacked package includes a conductive gang with gang legs electrically coupling a second component stacked over a first die to a package substrate. The first die is mounted over a die attach region of the package substrate and electrically coupled to the package substrate.

A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.

In a wiring member, an element connection portion, a plate connection portion, and an upper surface portion are at height positions different from one another. The element connection portion has a through hole, and the plate connection portion has a through hole and a chamfer. The upper surface portion which is not connected to another portion, has projections asymmetrically disposed on both side surfaces thereof. Owing to these features, the type, the orientation, and the front and the back of the wiring member can be easily distinguished. Accordingly, it is possible to prevent incorrect assembling of the wiring member in a semiconductor module.

A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.