To provide a novel Cu bonding wire that achieves a favorable FAB shape and a favorable bondability of the 2nd bonded part, and further achieves favorable bond reliability even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes: a core material of Cu or Cu alloy; and a coating layer containing conductive metal other than Cu formed on a surface of the core material, wherein the coating layer has a region containing Ni as a main component on a core material side, and has a region containing Au and Ni on a wire surface side, in a thickness direction of the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, a ratio C.sub.Au/C.sub.Ni of a concentration C.sub.Au (mass %) of Au to a concentration C.sub.Ni (mass %) of Ni relative to the entire wire is 0.02 or more and 0.7 or less, a concentration of Au at the surface of the wire is 10 atomic % or more and 90 atomic % or less, and at least one of the following conditions (i) and (ii) is satisfied: (i) a concentration of In relative to the entire wire is 1 ppm by mass or more and 100 ppm by mass or less (ii) a concentration of Ag relative to the entire wire is 1 ppm by mass or more and 500 ppm by mass or less.

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed.

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package preform includes a semiconductor chip and a plurality of binding wires. The semiconductor chip includes a plurality of welding spots, and the welding spots are electrically connected with corresponding conductive tracing wires by the binding wires. Each binding wire comprises a carbon nanotube composite wire, the carbon nanotube composite wire includes a carbon nanotube wire and a metal layer. The carbon nanotube wire consists of a plurality of carbon nanotubes spirally arranged along an axial direction an axial direction of the carbon nanotube wire.

Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having one or more wires that extend beyond a topmost component in the IC package assembly, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a substrate having a first side and a second side opposite the first side, an IC die having a first side and a second side opposite the first side, where the first side of the IC die faces the first side of the substrate, a wire electrically coupled with the IC die, where an end of the wire extends beyond a topmost component in the IC package assembly, and an overmold coupled with the topmost component. Other embodiments may be described and/or claimed.

An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Optionally, twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibit a sign of the torsional force applied thereto.

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

A bond wire has an outer layer formed of a conductive material and a core formed of a non-conductive material. The non-conductive material is blended with conductive fillers to enhance electrical and/or thermal conductivity characteristics of the bond wire.

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location.

A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.