H01L2224/43985

METHOD AND REAGENT FOR TREATING BARE COPPER WIRE AND SURFACE-TREATED COPPER WIRE
20180142358 · 2018-05-24 · ·

A method for treating a bare copper wire and a surface-treated copper wire includes applying a solution including a phosphoric acid-based chelating agent to a surface of a bare copper wire, and drying the copper wire having the solution including the phosphoric acid-based chelating agent attached on the surface thereof.

METHOD AND REAGENT FOR TREATING BARE COPPER WIRE AND SURFACE-TREATED COPPER WIRE
20180142358 · 2018-05-24 · ·

A method for treating a bare copper wire and a surface-treated copper wire includes applying a solution including a phosphoric acid-based chelating agent to a surface of a bare copper wire, and drying the copper wire having the solution including the phosphoric acid-based chelating agent attached on the surface thereof.

METHODS OF FORMING WIRE INTERCONNECT STRUCTURES AND RELATED WIRE BONDING TOOLS

A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to a position above the wire bond; (c) moving the wire bonding tool to contact the length of wire, at a position along the length of wire, to partially sever the length of wire at the position along the length of wire; and (d) separating the length of wire from a wire supply at the position along the length of wire, thereby providing a wire interconnect structure bonded to the bonding location.

Semiconductor device and its manufacturing method
09929120 · 2018-03-27 · ·

A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer. A wiring material (silver) including the redistribution layer can be inhibited from migrating.

Off substrate kinking of bond wire

An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Optionally, twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibit a sign of the torsional force applied thereto.

Semiconductor package structure and packaging method thereof

A semiconductor package structure includes a substrate, including first conductive pads and packaging pads opposite to the first conductive pads, one or more semiconductor chips stacking on the substrate, a molding compound encapsulating the semiconductor chips, first metal wires connecting the semiconductor chips to the packaging pads, a first metal pad on a side of the molding compound opposite to the substrate, and a second metal wire located in the molding compound and connecting the first metal pad to a chip-contact pad of a semiconductor chip of the semiconductor chips.

COPPER BONDING WIRE WITH ANGSTROM (Å) THICK SURFACE OXIDE LAYER

A copper wire having a diameter of 10 to 80 m is provided. The copper wire bulk material is 99.99 wt.-% pure copper or a copper alloy consisting of 10 to 1000 wt.-ppm of silver and/or of 0.1 to 3 wt.-% of palladium with copper as the remainder to make up 100 wt.-%, and the copper wire has a 0.5 to <6 nm thin circumferential surface layer of copper oxide.

SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGING METHOD THEREOF
20250096220 · 2025-03-20 ·

A semiconductor package structure includes a first substrate including first conductive pads, one or more semiconductor chips stacking on the first substrate, a second substrate on the semiconductor chips opposite to the first substrate, a molding compound on the first substrate and encapsulating the semiconductor chips and at least part of the second substrate, and a first metal wire located in the molding compound and connecting the second substrate to the semiconductor chips. The first conductive pads are on a side of the first substrate opposite to the semiconductor chips.

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
20170033074 · 2017-02-02 ·

A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A redistribution layer is formed in the polyimide resin film of a single layer. A wiring material (silver) including the redistribution layer can be inhibited from migrating.

MOLDED POWER DIE PACKAGE WITH VERTICAL INTERCONNECT

A power die package includes a power die having a plurality of bond pads at an upper surface of the power die. The package further includes a plurality of contact structures. A contact structure includes: a bond wire bonded to one of the plurality of bond pads and folded back to the bond pad to form a closed loop, or at least three bumps laterally spaced from one another and disposed on one or more bond pads; and a continuous longitudinally extended electrically conductive element connected to the at least three bumps in at least three contact positions. The conductive element bends away from the power die between pairs of consecutive contact positions. The package further includes a mold compound partially encapsulating the contact structure. The mold compound includes an outer surface facing away from the power die. The contact structure is partially exposed at the outer surface.