A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.

Disclosed is a package-on-package (PoP) assembly comprises a two-tiered windowed ball grid array (BGA) and a system on a chip (SoC) package. Window openings in the two tiers of the BGA are of different sizes to allow for wirebond landing pads on the first tier. A DRAM die is mounted to the BGA flipped over (i.e., wirebond pads facing the BGA package.) The DRAM die is wirebonded through the window in the BGA. For multi-channel systems and higher memory capacity, the DRAM die will have low-cost through-silicon vias (TSVs) that connect to stacked DRAM die(s). The stacked DRAM dies may be offset or rotated to align active TSVs with passive TSVs thereby enabling unique connections to certain DRAM dies in the stack.

A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.

A method for connecting an integrated circuit (IC) to a printed circuit board (PCB) can include the steps of fixing the IC and the PCB to a dielectric substrate. A single wire bond can be used to bond the IC to the PCB, and a ground plane can be established for the PCB. To minimize inductance losses at high frequency operation, a ground plane defect can be intentionally established by forming at least one opening in the ground plane. The opening can be rectangular when viewed in top plan, although the number of openings formed and opening geometry can be chosen according to the desired operating frequency of the device. The defect can allow for single wire bonding of the IC to the PCB in a manner which allows for high frequency operation without requiring the integration of additional matching network components on the IC and PCB.

A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

A semiconductor device has an interposer frame mounted over a carrier. A semiconductor die has an active surface and bumps formed over the active surface. The semiconductor die can be mounted within a die opening of the interposer frame or over the interposer frame. Stacked semiconductor die can also be mounted within the die opening of the interposer frame or over the interposer frame. Bond wires or bumps are formed between the semiconductor die and interposer frame. An encapsulant is deposited over the interposer frame and semiconductor die. An interconnect structure is formed over the encapsulant and bumps of the first semiconductor die. An electronic component, such as a discrete passive device, semiconductor die, or stacked semiconductor die, is mounted over the semiconductor die and interposer frame. The electronic component has an I/O count less than an I/O count of the semiconductor die.

A leadframe (300) for use in semiconductor devices, comprising an assembly pad (3010 having rectangular sides, the pad extending, on one pad side (301b), into a lead (302) and, on the opposite pad side (301a), into straps (350) oriented normal to the side (301a) and anchored in adjacent tie bars (313), strap surfaces having recesses (501, 502) suitable for interlocking with packaging materials. The leadframe further includes a plurality of leads (303) parallel to and alternating with the straps.

A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.