A method includes forming one or more trenches in a first substrate, forming one or more vias in a second substrate, aligning at least a first trench in the first substrate with at least a first via in the second substrate, and sealing the first substrate to the second substrate by filling the first via and the first trench with solder material using injection molded soldering.

A method includes forming one or more vias in a substrate, forming at least one liner on at least one sidewall of at least one of the vias, and filling said at least one via with solder material using injection molded soldering. The at least one liner may comprise a solder adhesion layer, a barrier layer, or a combination of a barrier layer and a solder adhesion layer.

A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

A micro bonding device, a bonding backplane and a display device are provided. The micro bonding device is configured to bond and connect two to-be-bonded electrodes, the micro bonding device includes a main part and multiple micro connectors protruding from the main part; the multiple micro connectors are arranged at intervals, and are configured to plugged with the two to-be-bonded electrodes. The micro bonding device, the bonding backplane and the display device can reduce repair difficulty of the micro electronic device, and prevent impact on surrounding already welded chips during repair.

To improve reliability by securing drop test characteristics or impact resistance in a semiconductor package. A semiconductor package includes a plurality of insulating layers and an under bump metal layer. The under bump metal layer is a metal layer connected to a bump. The under bump metal layer is partially exposed at the opening of the outermost layer among the plurality of insulating layers, and is connected to the bump at the exposed portion. The diameter of the under bump metal layer is larger than the diameter of the opening of the outermost layer. As a result, the under bump metal layer inhibits or reduces transmission of force to the land or RDL via the bump.

Some implementations herein provide a semiconductor package and methods of formation. The semiconductor package includes a semiconductor die having a first set of conductive structures connected with a substrate having a second set of conductive structures, where a profile of heights of the second set of conductive structures includes a curvature relative to a surface of the substrate. The curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced to the semiconductor die and/or the substrate during a reflow process that joins the semiconductor die and the substrate. By compensating for the warpage, a planarity of an interface region including solder joints between the first and second sets of conductive structures is increased. Increasing the planarity may reduce solder joint defects in the semiconductor package relative to another semiconductor package including another substrate having conductive structures without the profile having the curvature.

A semiconductor device includes a first semiconductor structure including a substrate, circuit devices on the substrate, and circuit interconnections on the circuit devices, and a second semiconductor structure on the first semiconductor structure and having first and second regions. The second semiconductor structure including a plate layer, gate electrodes stacked and spaced apart from each other on an upper surface of the plate layer in a vertical direction, extending by different lengths on the second region in a first direction intersecting the vertical direction, and including a gate contact region, interlayer insulating layers stacked alternately with the gate electrodes, a channel structure penetrating the gate electrodes and the interlayer insulating layers in the first region and extending in the vertical direction, contact plugs penetrating the gate electrodes in the second region, extending in the vertical direction, and electrically connecting the gate electrodes to a portion of the circuit interconnections, respectively.