A semiconductor device includes a first substrate, a second substrate spaced apart from the first substrate in a first direction, a first metal layer on the first substrate, a second metal layer on the first substrate and spaced apart from the first metal layer in a second direction, a first semiconductor element, and a second semiconductor element. The second substrate includes a main wiring and a signal wiring. The first semiconductor element includes a first electrode on the first metal layer, a second electrode connected to the main wiring, and a first gate electrode connected to the signal wiring. The second semiconductor element includes a third electrode on the second metal layer, a fourth electrode connected to the main wiring, and a second gate electrode connected to the signal wiring. During operation, current flows in wiring layers of the main wiring in opposite directions.

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device comprising at least one first thermally conductive structure proximate at least one of the first integrated circuit device, the second integrated circuit device, and the substrate; and a second thermally conductive structure disposed over the first thermally conductive structure(s), the first integrated circuit device, and the second integrated circuit device, wherein the first thermally conductive structure(s) have a lower electrical conductivity than an electrical conductivity of the second thermally conductive structure. The first thermally conductive structure(s) may be formed by an additive process or may be pre-formed and attached to at least one of the first integrated circuit device, the second integrated circuit device, and the substrate.

A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.

The purpose of the present invention is to provide an adhesive composition which allows an alignment mark to be recognized, ensures sufficient solder wettability of a joining section, and is excellent in suppression of void generation. The adhesive composition includes: a high-molecular compound (A); an epoxy compound (B) having a weight average molecular weight of 100 or more and 3,000 or less; and a flux (C); and inorganic particles (D) which have on the surfaces thereof an alkoxysilane having a phenyl group and which have an average, particle diameter of 30 to 200 nm, the flux (C) containing an acid-modified rosin.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.