A semiconductor device having a semiconductor module that includes a first conductor layer and a second conductor layer facing each other, a group of semiconductor elements that are formed between the first and second conductor layers, and are connected to the second conductor layer respectively via a group of conductor blocks, and a circuit board having one end portion thereof located in a space between the semiconductor elements and the second conductor layer. Each semiconductor element includes first and second main electrodes respectively formed on first and second main surfaces thereof, and a control electrode that is formed on the second main surface. The first main electrode is electrically connected to the first conductor layer. The second main electrode is electrically connected to the second conductor layer via the respective conductor block. The circuit board includes a first wiring layer electrically connected to the control electrodes of the semiconductor elements.

A display device includes: a substrate; sub-pixels on the substrate; data lines connected to the sub-pixels; a display driving circuit supplying data voltages to the data lines; and fan-out lines on the substrate and connecting the data lines and the display driving circuit. Each of the sub-pixels includes a first transistor including a first active layer on the substrate and including a silicon semiconductor and a first gate electrode on the first active layer, and a second transistor including a second active layer on the substrate and including an oxide semiconductor and a second gate electrode on the second active layer. The fan-out lines include first fan-out lines and second fan-out lines alternately arranged each other in one direction. The first fan-out lines are arranged on the same layer as the first gate electrode, and the second fan-out lines are arranged on the same layer as the second gate electrode.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures. After the following batch annealing, the fill nanoporous metal layer turns into pure bulk metal same as conductive interconnect structures due to the heat expansion of conductive interconnect structures and nanoporous metal densification.

A light-emitting device, including a circuit substrate, a first light-emitting diode, and a first fixing structure, is provided. The circuit substrate includes a substrate, a first pad, a flat layer, and a first electrical connection material. The first pad and the flat layer are located on the substrate. The flat layer has a first opening overlapping the first pad. The first electrical connection material is located in the first opening and is electrically connected to the first pad. The first light-emitting diode is located on the flat layer and in contact with the first electrical connection material. The first fixing structure is located between the first light-emitting diode and the flat layer. The vertical projection of the first fixing structure on the substrate is located in the vertical projection of the first light-emitting diode on the substrate.

A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.

A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.

A technique capable of improving a performance of a semiconductor detector is provided. The semiconductor detector is made based on injection of an underfill into a gap between a first semiconductor chip and a second semiconductor chip in a flip-chip connection state, but the underfill is not formed in periphery of a connection structure connecting a reading electrode pad and a gate terminal through a bump electrode.

Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

Described implementations provide wireless, surface mounting of at least two semiconductor die on die attach pads (DAPs) of the semiconductor package, where the at least two semiconductor die are electrically connected by a clip. A stress buffer layer may be provided on the clip, and a heatsink may be provided on the stress buffer layer. The heatsink may be secured with an external mold material.