H01L2224/73205

METHOD FOR PRODUCING A CIRCUIT ARRANGEMENT FOR AN ELECTRIC MACHINE, POWER SEMICONDUCTOR MODULE FOR A CIRCUIT ARRANGEMENT, AND CORRESPONDING CIRCUIT ARRANGEMENT
20250112214 · 2025-04-03 ·

A method for producing a circuit arrangement for an electric machine is provided. The circuit arrangement has at least one power input which is connectable to an electric energy storage device, at least one power semiconductor which is arranged in a power semiconductor module, and at least one power output which is connectable to an excitation coil of the electric machine, wherein the power input is electrically connected to a first power terminal of the power semiconductor module via an intermediate circuit of the circuit arrangement, and the power output is electrically connected to a second power terminal of the power semiconductor module via a control board of the circuit arrangement. A power semiconductor module for a circuit arrangement for an electric machine, and to a corresponding circuit arrangement is also provided.

Fingerprint sensor package and smart card having the same

A fingerprint sensor package includes: a first substrate including a core insulating layer including a first surface and a second surface and a through-hole, a first bonding pad on the second surface, and an external connection pad between an edge of the second surface and the first bonding pad; a second substrate in the through-hole and including a third surface and a fourth surface, and including first sensing patterns on the third surface, spaced apart in a first direction, and extending in a second direction, second sensing patterns spaced apart from each other in the second direction and extending in the first direction, and a second bonding pad on the fourth surface; a conductive support electrically connecting the first bonding pad and the second bonding pad and supporting the first substrate and the second substrate; a controller chip on the second substrate; and a molding layer on the second surface.

SENSOR PACKAGES
20250279323 · 2025-09-04 ·

In examples, semiconductor package comprises a semiconductor die having a device side including circuitry; a sensor on the device side; a metal ring on the device side to at least partially define a cavity vertically aligned with the sensor, with the metal ring having a top metal ring surface facing away from the semiconductor die and an exterior metal ring surface facing away from the sensor; and a metal pillar on the device side and having a top metal pillar surface facing away from the semiconductor die. The package also comprises a tie bar extending approximately parallel to the device side of the semiconductor die and coupled with solder to the top metal ring surface, with the tie bar exposed to a first exterior surface of the package. The package comprises a conductive member including a conductive terminal exposed to a second exterior surface of the package, a vertical member coupled to the conductive terminal and extending toward the first exterior surface of the package, and a horizontal member coupled to the vertical member, with the horizontal member soldered to the top metal pillar surface. The package comprises a mold compound contacting the exterior metal ring surface, with the mold compound absent from the cavity.

Semiconductor package including a plurality of semiconductor chips

A semiconductor package includes a base chip; semiconductor chips stacked on the base chip; bumps, a lowermost bump of the bumps disposed between the base chip and a lowermost semiconductor chip of the semiconductor chips, and each of the bumps except the lowermost bump respectively disposed between the semiconductor chips; organic material layers, a lowermost organic material layer of the organic material layers disposed between the base chip and the lowermost semiconductor chip, and each of organic material layers except the lowermost organic material layer respectively disposed between the plurality of semiconductor chips; underfill layers respectively surrounding the plurality of bumps, the underfill layers extending between the base chip and the lowermost semiconductor chip and between the semiconductor chips; and an encapsulant covering the base chip, the semiconductor chips, and the underfill layers.