A semiconductor die includes a semiconductor surface including circuitry electrically connected to top-level bond pads exposed on a top surface of the semiconductor die, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads. There is solder on at least the inner bond pads. A ring structure is positioned around a location of at least the inner bond pads.

A package that includes a substrate comprising a cavity, a first integrated device coupled to the substrate through a first plurality of pillar interconnects and a first plurality of solder interconnects, a second integrated device coupled to the substrate through a second plurality of pillar interconnects and a second plurality of solder interconnects, and a plurality of wire bonds coupled to the first integrated device and the second integrated device, wherein the plurality of wire bonds is located over the cavity of the substrate.

A MEMS package including a fixed frame, a moveable platform and elastic restoring members is provided. The moveable platform is moved with respect to the fixed frame. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position.

A MEMS package including a fixed frame, a moveable platform and elastic restoring members is provided. The moveable platform is moved with respect to the fixed frame. The elastic restoring members are connected between the fixed frame and the moveable platform, and used to restore the moved moveable platform to an original position.

A light-emitting diode (LED) package includes a first LED pixel including a plurality of first LED chips and a first pixel driving integrated circuit to drive the first LED chips according to an active matrix (AM) mode using entirety of a first frame period, wherein the first pixel driving integrated circuit includes a first storage area configured to store first frame data of each first LED chip, a second storage area configured to store duty ratio compensation data of each first LED chip, a pulse width modulation (PWM) data calculator configured to perform an arithmetic operation on the first frame data and the duty ratio compensation data to generate PWM data, and a PWM data generator configured to adjust an emission duty ratio based on the PWM data.

A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.

A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures includes a substrate and a superconducting trace. Additionally, each of the semiconductor structures includes a passivation layer and one or more under bump metal (UBM) structures. The cryogenic electronic package also includes one or more superconducting and/or conventional metal interconnect structures disposed between selected ones of the at least two superconducting semiconductor structures. The interconnect structures are electrically coupled to respective ones of the UBM structures of the semiconductor structures to form one or more electrical connections between the semiconductor structures. A method of fabricating a cryogenic electronic package is also provided.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

According to one embodiment, a semiconductor device includes chips and a first selection circuit. Each of the chips has at least first and second vias for transmitting at least first and second address signals, wherein these chips are stacked to be electrically connected via the first and second vias. The first selection circuit is provided in each chip, and includes a logic circuit that selects a chip based on at least the first and second address signals, and supplies a result of operating the first and second address signals to the subsequent chip.

An integrated device package is disclosed. The package can include a package substrate and an integrated device die having active electronic circuitry. The integrated device die can have a first side and a second side opposite the first side. The first side can have bond pads electrically connected to the package substrate by way of bonding wires. A redistribution layer (RDL) stack can be disposed on a the first side of the integrated device die. The RDL stack can comprise an insulating layer and a conductive redistribution layer. The package can include a passive electronic device assembly mounted and electrically connected to the RDL stack.