A method for processing a semiconductor wafer is provided. A semiconductor wafer includes a first main surface and a second main surface. Defects are generated inside the semiconductor wafer to define a detachment plane parallel to the first main surface. Processing the first main surface defines a plurality of electronic semiconductor components. A glass structure is provided which includes a plurality of openings. The glass structure is attached to the processed first main surface, each of the plurality of openings leaving a respective area of the plurality of electronic semiconductor components uncovered. A polymer layer is applied to the second main surface and the semiconductor wafer is split into a semiconductor slice and a remaining semiconductor wafer by cooling the polymer layer beneath its glass transition temperature along the detachment plane. The semiconductor slice includes the plurality of electronic semiconductor components.

Embodiments include systems in packages (SiPs) and a method of forming the SiPs. A SiP includes a package substrate and a first modularized sub-package over the package substrate, where the first modularized sub-package includes a plurality of electrical components, a first mold layer, and a redistribution layer. The SiP also includes a stack of dies over the package substrate, where the first modularized sub-package is disposed between the stack of dies. The SiP further includes a plurality of interconnects coupled to the stack of dies, the first modularized sub-package, and the package substrate, wherein the redistribution layer of the first modularized sub-package couples the stack of dies to the package substrate with the plurality of interconnects. The SiP may enable the redistribution layer of the first modularized sub-package to couple the electrical components to the stacked dies and the package substrate without a solder interconnect.

Disclosed are a power module and a method for manufacturing the same. A power module according to an embodiment of the present disclosure includes: a first substrate; a second substrate disposed spaced apart from the first substrate and including at least one metal layer; at least one chip disposed between the first substrate and the second substrate and in electrical contact with the metal layer; and a third substrate configured to be disposed spaced apart from the first substrate and the second substrate, electrically connect the chip and at least one external input terminal, include one or more conductive patterns each of which is connected to one of the at least one lead frame, and be formed in a multi-layer structure such that the one or more conductive patterns are not short-circuited to each other.

Semiconductor module including a semiconductor and including a shaped metal body that is electrically contacted by the semiconductor, for forming a contact surface for an electrical conductor, wherein the shaped metal body is bent or folded. A method is also described for establishing electrical contacting of an electrical conductor on a semiconductor, said method including the steps of: fastening a bent or folded shaped metal body of a constant thickness to the semiconductor by means of a first fastening method and then fastening the electrical conductor to the shaped metal body by means of a second fastening method.

Semiconductor module having a first substrate, a second substrate and a spacer distancing the substrates from each other, wherein the spacer is formed by at least one elastic shaped metal body.

A semiconductor device disclosed herein may include: a semiconductor element including an electrode on a surface of the semiconductor element; and a terminal bonded to the electrode via a bonding material, wherein the electrode may include a protrusion portion that protrudes toward the terminal and is in contact with the bonding material.

A method of die and clip attachment includes providing a clip, a die and a substrate, laminating a sinterable silver film on the clip and the die, depositing a tack agent on the substrate, placing the die on the substrate, placing the clip on the die and the substrate to create a substrate, die and clip package, and sintering the substrate, die and clip package.

A semiconductor device includes: a substrate; a semiconductor element that disposed on the upper surface of the substrate; a sealing portion that seals the substrate and the semiconductor element; a first lead frame that has one end in contact with a upper surface of the first conductive layer at an end extending in the side direction of the upper surface of the substrate in the sealing portion, and has the other end exposed from the sealing portion; a first conductive bonding material that bonds between the upper surface of the first conductive layer and the lower surface side of the one end portion of the first lead frame at the end portion of the substrate, and has electrical conductivity.

A semiconductor device may include: an upper conductive plate, a middle conductive plate, and a lower conductive plate which are stacked on each other; a first semiconductor chip located between the upper and middle conductive plates and electrically connected to both the upper and middle; a second semiconductor chip located between the middle and lower conductive plates and electrically connected to both the middle and lower conductive plates; and an encapsulant encapsulating the first and second semiconductor chips and integrally holding the upper, middle and lower conductive plates. The middle conductive plate may include a main portion joined to the first and second semiconductor chips within the encapsulant and an exposed portion exposed outside on a surface of the encapsulant. A thickness of the exposed portion may be equal to or greater than a thickness of the main portion.

A package device preventing solder overflow provides a space or structure to limit the location of the solder when dispensing the solder. The package device includes a die, an anti-overflow layer, a first pin, a second pin, and a package body. The die has an electrode pad. The anti-overflow layer is disposed on a top surface of the electrode pad and has an opening to expose the top surface of the electrode pad. The first pin is connected to the die. The second pin is soldered to the electrode pad of the die through the opening of the anti-overflow layer. The package body covers the die.