A semiconductor module according to the present disclosure includes a circuit board having a first surface and a second surface, a first semiconductor device mounted on the first surface of the circuit board, a second semiconductor device mounted on the second surface of the circuit board, a first heat dissipation substrate placed on the top of the first semiconductor device, and a second heat dissipation substrate placed on the top of the second semiconductor device. The first heat dissipation substrate is coupled to a second surface of the first semiconductor device and the second heat dissipation substrate is coupled to a second surface of the second semiconductor device.

A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

A semiconductor module includes: a first substrate having a first insulating substrate and a first conductor layer; a power device part having a first electrode, a second electrode and a gate electrode; a second substrate having a second insulating substrate, a second conductor layer and a third conductor layer wherein a hole is formed in the second insulating substrate, the second conductor layer has a bonding portion and a surrounding wall portion; an inner resin portion; a control IC; and an outer resin portion, wherein the first substrate, the power device part, the second substrate and the control IC are stacked in this order, a connector is disposed in the inside of the hole, and the gate electrode is electrically connected to a control signal output terminal of the control IC through a connector.

A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

A high voltage (HV) converter implemented on a printed circuit board (PCB) includes a double diffused metal oxide semiconductor (DMOS) package comprising a lead frame and a main DMOS chip. The lead frame includes a gate section electrically connected to a gate electrode of the main DMOS chip, a source section electrically connected to a source electrode of the main DMOS chip and a drain section electrically connected to a drain electrode of the main DMOS chip. The PCB layout includes a large area source copper pad attached to and overlapping the source section of the DMOS package to facilitate cooling and a small area drain copper pad attached to and overlapping the drain section of the DMOS package to reduce electromagnetic interference (EMI) noise.

A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

In described examples, a microelectronic device includes a microelectronic die with a die attach surface. The microelectronic device further includes a nanoparticle layer coupled to the die attach surface. The nanoparticle layer may be in direct contact with the die attach surface, or may be coupled to the die attach surface through an intermediate layer, such as an adhesion layer or a contact metal layer. The nanoparticle layer includes nanoparticles having adjacent nanoparticles adhered to each other. The microelectronic die is attached to a package substrate by a die attach material. The die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles.

Electronic packages are formed from a generally planar leadframe having a plurality of leads coupled to a GaN-based semiconductor device, and are encased in an encapsulant. The plurality of leads are interdigitated and are at different voltage potentials.