Various embodiments may provide a semiconductor package. The semiconductor package may include a semiconductor chip, a first mold compound layer at least partially covering the semiconductor chip, and a redistribution layer over the first mold compound layer, the redistribution layer including one or more electrically conductive lines in electrical connection with the semiconductor chip. The semiconductor package may additionally include a second mold compound layer over the redistribution layer, and an antenna array over the second mold compound layer, the antenna array configured to be coupled to the one or more electrically conductive lines.

Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

A packaged semiconductor includes an electrically insulating encapsulant body having an upper surface, a first semiconductor die encapsulated within the encapsulant body, the first semiconductor die having a main surface with a first conductive pad that faces the upper surface of the encapsulant body, a second semiconductor die encapsulated within the encapsulant body and disposed laterally side by side with the first semiconductor die, the second semiconductor die having a main surface with a second conductive pad that faces the upper surface of the encapsulant body, and a first conductive track that is formed in the upper surface of the encapsulant body and electrically connects the first conductive pad to the second conductive pad. The encapsulant body includes a laser activatable mold compound.

Disclosed are a system-on-chip integrated packaging structure, a manufacturing method therefor and a three-dimensional stacked device. The system-on-chip integrated packaging structure includes: a substrate, a chip, a first electrical connection structure and a second electrical connection structure. A front surface of the substrate is provided with a recess and a via welding pad, and a back surface of the substrate is provided with a conductive via extending to the via welding pad. The chip is embedded in the recess, and a chip welding pad is disposed on a surface of the chip away from a bottom surface of the recess. Different chips may be electrically connected by means of the first electrical connection structure and the second electrical connection structure, which is conducive to form a three-dimensional stacked structure with high-density interconnection, miniaturized packaging and thinning.

A method may include forming a first atomic layer deposition (ALD) bonding layer on a surface of a first semiconductor device, and forming a second ALD bonding layer on a surface of a second semiconductor device. The method may include joining the first semiconductor device and the second semiconductor device via the first ALD bonding layer and the second ALD bonding layer. The method may include performing an annealing operation to fuse the first ALD bonding layer and the second ALD bonding layer and form a single ALD bonding layer that bonds the first semiconductor device with the second semiconductor device.

A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

What is disclosed is a module arrangement. An antenna device and at least one electronic component are arranged next to each other and within one plane between a top side and a bottom side of the module arrangement. A shielding device which has a shielding effect relative to electromagnetic signals is located between the antenna device and the electronic component. Additionally, a method for manufacturing a module arrangement is disclosed.

A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

A method includes forming an insulating layer over a package. The package has a plurality of locations where openings are subsequently formed. A first laser shot is performed, location by location, on each of the locations across the package. A first laser spot of the first laser shot overlaps with each of the locations. The first laser shot removes a first portion of the insulating layer below the first laser spot. Another laser shot is performed, location by location, on each of the locations across the package. Another laser spot of the another laser shot overlaps with each of the locations. The another laser shot removes another portion of the insulating layer below the another laser spot. Performing the another laser shot, location by location, on each of the locations across the package is repeated multiple times, until desired portions of the insulating layer are removed.