In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and the source that are located on a first surface of the second die and a drain that is located on a second surface of the second die that is opposite the first surface.

An embodiment related to a package is disclosed. The package includes a component mounted to a die attach region on a package substrate. A passive component with first and second passive component terminals is vertically attached to the package substrate. An encapsulant is disposed over the package substrate to encapsulate the package. In one embodiment, an external component is stacked above the encapsulant and is electrically coupled to the encapsulated package.

In one embodiment, a method can include coupling a gate and a source of a first die to a lead frame. The first die can include the gate and the source that are located on a first surface of the first die and a drain that is located on a second surface of the first die that is opposite the first surface. In addition, the method can include coupling a source of a second die to the drain of the first die. The second die can include a gate and a drain that are located on a first surface of the second die and the source that is located on a second surface of the second die that is opposite the first surface.

In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments.

A semiconductor package comprises a lead frame, two or more low side field-effect transistors (FETs), two or more high side FETs, two or more metal clips, a metal slug, an integrated circuit (IC) controller, and a molding encapsulation. A method for fabricating a semiconductor package comprising the steps of providing a lead frame comprising die paddles; attaching transistors to the die paddles respectively; mounting metal clips; mounting a metal slug and a controller, applying bonding wires; forming a molding encapsulation; and applying a singulation process.

A semiconductor package includes: a substrate having a metallic surface; a semiconductor die metallurgically bonded to the metallic surface of the substrate by a first solder joint; and a solder wetting structure metallurgically welded to the metallic surface of the substrate outside a perimeter of the semiconductor die and adjacent to one or more side faces of the semiconductor die. Excess solder squeezed out from under the semiconductor die is metallurgically bonded to the solder wetting structure. Methods of producing the semiconductor package and solder wetting structure are also described.