A method and device for bonding chips onto a substrate or onto further chips. The chips are bonded onto the substrate or the further chips by means of a direct bond.

A semiconductor package includes a first package component comprising: a first semiconductor die; a first encapsulant around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package further includes a second package component bonded to the first package component, wherein the second package component comprises a second semiconductor die; a heat spreader between the first semiconductor die and the second package component; and a second encapsulant between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat spreader.

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

Semiconductor devices are provided in which a first semiconductor device is bonded to a second semiconductor device. The bonding may occur at a gate level, a gate contact level, a first metallization layer, a middle metallization layer, or a top metallization layer of either the first semiconductor device or the second semiconductor device.

A package structure includes a first die, a die stack structure, a support structure and an insulation structure. The die stack structure is bonded to the first die. The support structure is disposed on the die stack structure. A width of the support structure is larger than a width of the die stack structure and less than a width of the first die. The insulation structure at least laterally wraps around the die stack structure and the support structure.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.