An LED module includes light emission windows; LED cells corresponding to the light emission windows, the LED cells each including a lower and upper light emitting structure, the lower light emitting structure having an upper surface with first and second regions and having a first conductivity-type semiconductor layer, the upper light emitting structure being on the first region of the lower light emitting structure and having a second conductivity-type semiconductor layer, the LED cells including an active layer between the first and second conductivity-type semiconductor layers; a protective insulating film on a side surface of the lower light emitting structure and on the second region; a light blocking film on the protective insulating film, between the LED cells; a gap-fill insulating film on the protective insulating film between the LED cells and contacting a side surface of the upper light emitting structure; a first electrode; and a second electrode.

3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

3D integrated circuit (3DIC) device architecture is disclosed for monolithically heterogeneous integration of III-V devices over Si-CMOS devices with high-quality (HQ) integrated passives devices (IPD) or re-distributed layers (RDL). In addition, a thermal spreader may be added over the upper III-V tier to enhance device power performance (e.g., PAE for PA) and device reliability (e.g., with a reduced Tj/junction temperature).

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A bonded structure is disclosed. The bonded structure can include a first element that includes a first conductive feature and a first nonconductive region. The first conductive feature can include a fine grain metal that has an average grain size of 500 nm or less. The bonded structure can include a second element that includes a second conductive feature and a second nonconductive region. The first conductive feature is directly bonded to the second conductive feature without an intervening adhesive, and the second nonconductive region is directly bonded to the second nonconductive region without an intervening adhesive.

A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.

A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level. These die pairs are formed using wafer-to-wafer bonding technology, where the wafers may be bonded to each other when they are of full thickness. Once bonded, respective inactive surfaces of the wafers may be thinned and then the die pairs diced from the wafers to form a completed memory module. When the wafers are bonded face to face, they compensate each other, mechanically resulting in the die pair having a minimum warpage.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

A method of manufacturing a semiconductor device, includes: alternately stacking a first film and a second film on a surface of a semiconductor substrate to form a multilayer film; partially removing the multilayer film to form stacks and a depression between one of the stacks and another one of the stacks and expose an end portion of the surface; forming a first insulating film to fill the depression; forming a first protective film on the stacks, the first insulating film, and the end portion; forming a second insulating film on the first protective film, the second insulating film overlapping at least a part of the other one of the stacks and the end portion; and removing the second insulating film in a thickness direction using chemical mechanical polishing.