Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first interconnect layer including first interconnects is formed above a first substrate. A first bonding layer including first bonding contacts is formed above the first interconnect layer, such that each first interconnect is in contact with a respective first bonding contact. A second interconnect layer including second interconnects is formed above a second substrate. A second bonding layer including second bonding contacts is formed above the second interconnect layer, such that at least one second bonding contact is in contact with a respective second interconnect, and at least another second bonding contact is separated from the second interconnects. The first and second substrates are bonded in a face-to-face manner, such that each first bonding contact is in contact with one second bonding contact at a bonding interface.

A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

A semiconductor device and method of manufacture are provided wherein semiconductor devices are attached over a semiconductor substrate. An opening is formed within metallization layers over the semiconductor substrate and the semiconductor substrate, and an encapsulant is placed to fill the opening. Once the encapsulant is placed, the semiconductor substrate is singulated to separate the devices. By recessing the material of the metallization layers and forming the opening, delamination damage may be reduced or eliminated.

A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.