A method for forming a three-dimensional memory device includes forming, on a first side of a first substrate, a plurality of semiconductor devices including at least first and second semiconductor devices, a first interconnect layer, and a shallow trench isolation (STD structure between the semiconductor devices, and forming, on a second substrate, a memory array including a plurality of memory cells and a second interconnect layer. The method includes connecting the first and second interconnect layers and forming an isolation trench through the first substrate and exposing a portion of the STI structure. The isolation trench is formed through a second side of the first substrate that is opposite to the first side. The method includes disposing an isolation material to form an isolation structure in the isolation trench and performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

A substrate bonding system in one manner of the present disclosure includes a surface treatment module configured to perform plasma processing on a surface of a substrate. The substrate bonding system includes a deposition module coupled to the surface treatment module such that the substrate is transferred to the deposition module without being exposed to atmosphere, the deposition module being configured to perform a deposition process on the substrate on which the plasma processing is performed in the surface treatment module. The substrate bonding system includes a bonding module coupled to the deposition module such that the substrate is transferred to the bonding module without exposing the substrate to the atmosphere, the bonding module being configured to bond substrates on which the deposition process is performed in the deposition module, to form a bonded body.

A method of liquid assisted micro cold binding is provided. The method includes: forming a conductive pad on the substrate in which the conductive pad consists essentially of indium; forming a liquid layer on the conductive pad; placing a micro device having an electrode facing the conductive pad over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad in which the electrode consists essentially of indium; and evaporating the liquid layer such that the electrode is bound to the conductive pad and is in electrical contact with the conductive pad.

Certain embodiments provide a method for manufacturing a semiconductor device including forming a first interconnection layer having a first conductive layer and a first insulating layer which are exposed from a surface of the first interconnection layer, forming a second interconnection layer having a second conductive layer and a second insulating layer which are exposed from a surface of the second interconnection layer, forming a first non-bonded surface on the surface of the first insulating layer by making a partial area of the surface of the first insulating layer lower than the surface of the first conductive layer, the partial area containing surroundings of the first conductive layer, and connecting the surface of the first conductive layer and the surface of the second conductive layer and bonding the surface of the first insulating layer excluding the first non-bonded surface and the surface of the second insulating layer.

A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

A production of voids between substrates is prevented when the substrates are bonded together, and the substrates are bonded together at a high positional precision while suppressing a strain. A method for bonding a first substrate and a second substrate includes a step of performing hydrophilization treatment to cause water or an OH containing substance to adhere to bonding surface of the first substrate and the bonding surface of the second substrate, a step of disposing the first substrate and the second substrate with the respective bonding surfaces facing each other, and bowing the first substrate in such a way that a central portion of the bonding surface protrudes toward the second substrate side relative to an outer circumferential portion of the bonding surface, a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate at the respective central portions, and a step of abutting the bonding surface of the first substrate with the bonding surface of the second substrate across the entirety of the bonding surfaces, decreasing a distance between the outer circumferential portion of the first substrate and an outer circumferential portion of the second substrate with the respective central portions abutting each other at a pressure that maintains a non-bonded condition.

A semiconductor device includes a first laminated body and a second laminated body. The first laminated body includes sequentially a first element, a first wiring layer, and a first connection layer that includes a first junction electrode, on a main surface of a first substrate. The second laminated body includes sequentially a second element, a second wiring layer, and a second connection layer that includes a second junction electrode, on a main surface of a semiconductor substrate. The first laminated body and the second laminated body are bonded by directly bonding the first junction electrode and the second junction electrode with the two junction electrodes facing each other. A space region is formed at a part of a junction interface between the first laminated body and the second laminated body.

A stacked device includes a stacked structure in which a plurality of semiconductors are electrically connected to each other, the semiconductor includes a surface on which a plurality of terminals are provided, the plurality of terminals include a terminal that bonds and electrically connects the semiconductors to each other and a terminal that bonds the semiconductors to each other and does not electrically connect the semiconductors to each other, an area ratio of the plurality of terminals on the surface of the semiconductor is 40% or higher, and an area ratio of the terminals that bond and electrically connect the semiconductors to each other among the plurality of terminals is lower than 50%.