A bonding method includes a substrate holding step of holding substrates (W1, W2), a first contact step of bringing central portions of the substrates (W1, W2) into contact with each other, a second contact step of, enlarging a contact area between the substrates (W1, W2) from central portions toward peripheral portions of the substrates (W1, W2), and a bonding step of, bonding the substrates (W1, W2) to each other by pressing only a peripheral portion of the substrate (W1) against a peripheral portion of the substrate (W2) while the substrates (W1, W2) are in contact with each other over entire bonding surfaces.

The method is carried out of a first substrate having a first layer made of a first material with a second substrate having a second layer made of a second material, the first material and the second material being of different natures and selected from alloys of elements of columns III and V, the method having the steps of: a) providing the first substrate and the second substrate, b) bringing the first substrate into contact with the second substrate so as to form a bonding interface between the first layer and the second layer, c) performing a first heat treatment at a first predefined temperature, d) thinning one of the substrates, e) depositing, at a temperature less than or equal to the first predefined temperature, a barrier layer, on the thinned substrate, and f) performing a second heat treatment at a second predefined temperature, greater than the first predefined temperature.

In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 1?10.sup.?2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

A packaging method and a package structure are provided. The packaging method includes the following steps. Firstly, a plurality of chips are disposed on a carrying surface of a carrying board for chip redistribution. Each of the chips includes a first side connected to the carrying surface and a second side opposite to the first side, and the second side is provided with at least one chip connecting member. Next, a base structure is provided. The base structure has a bonding surface provided with a plurality of predetermined areas for bonding the chips respectively, and each of the predetermined regions has at least one electrically connecting structure formed therein. Lastly, an encapsulating material is applied to integrate the base structure, the chips, and the carrying board into a unitary structure under specific hot pressing conditions.

A method of making an integrated circuit device with a diamond heat spreader including one or more integrated circuit (IC) devices in a semiconductor material and bonding one or more diamond layers. A device may comprise one or more integrated circuit (IC) devices in a semiconductor material thinner than 100 micrometers and one or more diamond layers of thickness up to 2000 micrometers bonded to the semiconductor material.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

Embodiments of a three-dimensional (3D) memory device and fabrication methods are disclosed. In some embodiments, the 3D memory device includes a peripheral circuitry formed on a first substrate. The peripheral circuitry includes a plurality of peripheral devices on a first side of the first substrate, a first interconnect layer, and a deep-trench-isolation on a second side of the first substrate, wherein the first and second sides are opposite sides of the first substrate and the deep-trench-isolation is configured to provide electrical isolation between at least two neighboring peripheral devices. The 3D memory device also includes a memory array formed on a second substrate. The memory array includes at least one memory cell and a second interconnect layer, wherein the second interconnect layer of the memory array is bonded with the first interconnect layer of the peripheral circuitry, and the peripheral devices are electrically connected with the memory cells.

In an embodiment, a wafer bonding system includes a chamber, a gas inlet and a gas outlet configured to control a pressure of the chamber to be in a range from 110.sup.2 mbar to 1520 torr, a first wafer chuck having a first surface to support a first wafer, and a second wafer chuck having a second surface to support a second wafer, the second surface being opposite the first surface, the second wafer chuck and the first wafer chuck being movable relative to each other, wherein the second surface that supports the second wafer is divided into zones, wherein a vacuum pressure of each zone is controlled independently of other zones.

A device for aligning and placing electrical components includes a first stage to support at least one first electrical component, each first electrical component having a plurality of conductive surfaces on a side opposite the first stage, a second stage to support at least one second electrical component, each second electrical component having a plurality of conductive surfaces on a side opposite the second stage, a voltage source to produce a voltage between the conductive surfaces of the first electrical components and conductive surfaces of the second electrical components, and a controller to control relative motion between the first stage and the second stage, and to align corresponding ones of the plurality of conductive surfaces of the first electrical component with corresponding ones of the plurality of conductive surfaces on the second electrical component at least partially on the basis of an electrostatic force therebetween.