Patent classifications
H01L2224/80095
Microstructure modulation for metal wafer-wafer bonding
A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.
Integrated circuit package and method
In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
Integrated circuit package and method
In an embodiment, a package includes: an interposer having a first side; a first integrated circuit device attached to the first side of the interposer; a second integrated circuit device attached to the first side of the interposer; an underfill disposed beneath the first integrated circuit device and the second integrated circuit device; and an encapsulant disposed around the first integrated circuit device and the second integrated circuit device, a first portion of the encapsulant extending through the underfill, the first portion of the encapsulant physically disposed between the first integrated circuit device and the second integrated circuit device, the first portion of the encapsulant being planar with edges of the underfill and edges of the first and second integrated circuit devices.
Substrate bonding apparatus and substrate bonding method
A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.
Substrate bonding apparatus and method of manufacturing semiconductor device by using the same
A substrate bonding method and apparatus are described. The substrate bonding apparatus is used to bond a first substrate to a second substrate. The bonding apparatus includes a first bonding chuck configured to hold the first substrate on a first surface of the first bonding chuck; a second bonding chuck configured to hold the second substrate on a second surface of the second bonding chuck, the second surface facing the first surface of the first bonding chuck; a seal arranged between the first bonding chuck and the second bonding chuck and adjacent to at least one edge of the first substrate and at least one edge of the second substrate; and a process gas supply device configured to supply a process gas to a bonding space surrounded by the seal.
MICROSTRUCTURE MODULATION FOR METAL WAFER-WAFER BONDING
A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.
Wafer-bonding structure and method of forming thereof
A method of forming a wafer-bonding structure includes a wafer-bonding step, a through silicon via (TSV) forming step, and a forming bonding pad step. In the wafer-bonding step, at least two wafers are corresponding to and bonded to each other by bonding surfaces thereof. In the TSV forming step, a TSV structure is formed on at least one side of a seal ring structure of one of the wafers, a conductive filler is disposed in the TSV structure, and the TSV structure is overlapped the side of one of the seal ring structure of one of the wafers and a portion of a seal ring structure of another one of the wafers. In the forming bonding pad step, a bonding pad is formed on an outer surface which is relative to the bonding surface of the wafer with the TSV structure, so as to form the wafer-bonding structure.
BONDING METHOD FOR COPPER-COPPER METAL
The present disclosure belongs to the technical field of three-dimensional packaging, and in particular relates to a bonding method for a copper-copper metal. The bonding method includes: subjecting a copper-plated surface of a clean copper-plated substrate to pretreatment with hydrazine hydrate under a protective atmosphere, to obtain a copper-plated substrate to be bonded, where the copper-plated surface is kept at 50? C. to 90? C.; and subjecting a plurality of the copper-plated substrates to be bonded to pressurized bonding at 200? ? C. to 300? ? C. under the protective atmosphere.
Microstructure modulation for metal wafer-wafer bonding
A three-dimensional (3D) bonded semiconductor structure is provided in which a first bonding oxide layer of a first semiconductor structure is bonded to a second bonding oxide layer of a second semiconductor structure. Each of the first and second bonding oxide layers has a metallic bonding structure embedded therein, wherein each metallic bonding structure contains a columnar grain microstructure. Furthermore, at least one columnar grain extends across a bonding interface that is present between the metallic bonding structures. The presence of the columnar grain microstructure in the metallic bonding structures, together with at least one columnar grain microstructure extending across the bonding interface between the two bonded metallic bonding structures, can provide a 3D bonded structure having mechanical bonding strength and electrical performance enhancements.
SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD
A substrate bonding apparatus that brings a part of a surface of a first substrate and a part of a surface of a second substrate into contact to form contact regions at the parts, and then enlarges the contact regions to bond the first substrate and the second substrate includes: a temperature adjusting unit that adjusts a temperature of at least one of the first substrate and the second substrate such that positional misalignment between the first substrate and the second substrate does not exceed a threshold at least in a course of enlargement of the contact regions.