H01L2224/80136

METHOD OF MANUFACTURING STACKED WAFER ASSEMBLY
20190081021 · 2019-03-14 ·

A stacked wafer assembly is made by forming a grid of grooves corresponding to projected dicing lines in a face side of each of two wafers, thereby forming demarcated areas on the face side of each of the two wafers. One of the wafers is installed with demarcated areas face upwardly, and thereafter liquid is supplied to the demarcated areas in a quantity just enough to stay on upper surfaces of the demarcated areas without overflowing. The other wafer is placed over the one wafer with demarcated areas of the other wafer facing the respective demarcated areas of the one wafer, thereby bringing respective central positions of the facing demarcated areas of the wafers into self-alignment with each other under the surface tension of the liquid sandwiched between the facing demarcated areas. The liquid is removed to bring the wafers into intimate contact with each other.

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Hybrid bonding systems and methods for semiconductor wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Sacrificial Alignment Ring And Self-Soldering Vias For Wafer Bonding
20180286836 · 2018-10-04 ·

A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
20180254267 · 2018-09-06 · ·

A method of manufacturing a semiconductor device that includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected through a first joining material to the conductive pattern, a second semiconductor chip with a rectangular shape disposed on the conductive pattern separated from the first semiconductor chip and connected through a second joining material to the conductive pattern, a terminal disposed above the semiconductor chips, respectively connected to the first and second semiconductor chips through third and fourth joining materials, the terminal having a through-hole above a place between the first and second semiconductor chips, the method including a positioning step in which the first and second semiconductor chips are respectively positioned at at least three positioning places, and at least one of the positioning places is positioned with a positioning member inserted into the through-hole.

Semiconductor device, method of manufacturing a semiconductor device, and positioning jig
09991242 · 2018-06-05 · ·

A semiconductor device has a plurality of small-sized semiconductor chips disposed between an insulated circuit board having a conductive pattern and a terminal. The semiconductor device exhibits a high accuracy in positioning the semiconductor chips. The semiconductor device includes an insulated circuit board having a conductive pattern, a first semiconductor chip with a rectangular shape connected to the conductive pattern through a first joining material, a second semiconductor chip with a rectangular shape, disposed on the conductive pattern separated from the first semiconductor chip and connected to the conductive pattern through a second joining material, and a terminal disposed above the first semiconductor chip and the second semiconductor chip, connected to the first semiconductor chip through a third joining material, and connected to the second semiconductor chip through a fourth joining material. The terminal has a through-hole above a place between the first semiconductor chip and the second semiconductor chip.

METHOD AND SYSTEM OF PERFORMING COLLECTIVE DIE-TO-WAFER BONDING

The present invention relates to a method of performing collective die-to-wafer bonding. The method comprises the steps of: providing a carrier wafer having a back side and a bonding side opposite the back side and comprising on the bonding side one or more pockets that each are configured for accommodating a die, respectively, providing a target substrate comprising an integrated circuit, hereinafter IC, and one or more target bonding pads for connecting the one or more dies to the IC, placing one or more dies in the one or more pockets, respectively, and bonding the one or more dies placed in the one or more pockets to the tar-get substrate by bringing the one or more dies into contact with the one or more target bonding pads.

Hybrid Bonding Systems and Methods for Semiconductor Wafers

Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.

Inorganic light emitting diode, display module and manufacturing method thereof

An inorganic light emitting diode is disclosed. The inorganic light emitting diode includes a first semiconductor layer, a second semiconductor layer having a light emitting surface composed of four sides, an active layer disposed between the first semiconductor layer and the second semiconductor layer, a first electrode coupled to the first semiconductor layer, and a second electrode coupled to the second semiconductor layer, wherein the light emitting surface has a trapezoid shape in which two opposing sides are symmetric with respect to each other.